10. Outline
• Introduction
• Objectives & Features
• Circuit Design and Simulated Results
• Hardware Implementation
• Conclusions and Future Work
11. Circuit Design and Simulated Results
• Neuron Emulator Specification and Headstage Circuit
Cell Model with AP Generation
Simplified Model for the Neuron Cell
Simplified AP Generator
• Headstage Amplifiers
Neuron Emulator in C_C
Neuron Emulator in V_C
• Comparison with CV-7B Headstage
CV-7B Headstage in C_C
CV-7B Headstage in V_C
12. Neuron Emulator and Headstage
Circuit Specification
Membrane model AP model Threshold range Voltage sources Electrode Headstage
Rm Cm τm Rap Cap τap Vth fap Vspike Vrest Re Iclamp
5
MΩ
10
pF
0.05
ms
5
KΩ
1
μF
5
ms
-60~-30
mV
1~10
Hz
20
mV
-90
mV
22
MΩ
6~12
nA
Siz
e τap
Speed Vp-p
13. Cell Model with AP Generation (1)
)()1)(()1)((
1
2
1
2
43
4
1
2
43
4
R
R
V
R
R
RR
R
V
R
R
RR
R
VV KrestNaap −++
+
++
+
= KNarest VVV −+=
Na K
adder
4321 RRRR ===
Na
K
Bigger
Bigger
14. Simplified Model for the Neuron Cell
Switch phase Time constant Voltage sources
φde φre τNa τK VpK VpNa Vrest
High Low 0.05 ms 0.15 ms
32 mV 72 mV 0 V
Low High 0.25 ms 0.45 ms
linear
nonlinear
φde
φre
slower
15. Simplified AP Generator(1)
Membrane model AP model Voltage sources Electrode
Rm Cm τm Rap Cap τap Vspike Vrest Re
5 MΩ 10 pF 0.05 ms 5 KΩ 1 μF 5 ms 20 mV -90 mV 22 MΩ
Smaller
Bigger
17. Circuit Design and Simulated Results
• Neuron Emulator Specification and Headstage Circuit
Cell Model with AP Generation
Simplified Model for the Neuron Cell
Simplified AP Generator
• Headstage Amplifiers
Neuron Emulator in C_C
Neuron Emulator in V_C
• Comparison with CV-7B Headstage
CV-7B Headstage in C_C
CV-7B Headstage in V_C
19. Neuron Emulator circuit for
current clamp experimentcurrent clamp experiment.
m
restclamp
e
clampe
clamp
R
VV
R
VV
I
−
=
−
=
mclamprestclamp RIVV +=
of
if
I
R
R
A
−
=
Shaded areas will be implemented on a microcontroller
(see Appendix A)
20. Neuron Emulator parametric analysis
circuit simulation results in C_C
Condition Iclamp = 10 nA, fap = 6.25 Hz, τap = 5 ms
Probe point Vclamp Ve
Vpp
Vm~VM
110 mV
-40~70 mV
110 mV
180~290 mV
Condition Vth = -60 ~ -30 mV → Iclamp = 6 ~12 nA, τap = 5 ms
Iclamp 5 nA 6 nA 12 nA 13 nA
Vclamp
-65 mV
-60 mV -30 mV
-25 mVVrest
Vap / Vm~VM -60~50 mV -30~80 mV
Vpp 0 V 110mV 0 V
fap 0 Hz 1 Hz 10 Hz 0 Hz
1Hz
10Hz
21. Neuron Emulator for
voltage clamp experimentvoltage clamp experiment.
Shaded areas will be implemented on a
microcontroller
apclamp
eap
t
eclamp
e
QQ
dtRIRI
RC
+=
+∫ )(
1
0int
eapeclampclampe RIRIVV +=−
m
e
V
R
R
A
−
=
22. Neuron Emulator parametric analysis
circuit simulation result in V_C
Iclamp = 10 nA, fap = 6.67 Hz, τap = 5 ms
Qap
110 pC 2.42 mV
∫
T
apdtV
0
Condition τap = 5 ms
Vrest / Vclamp -65 mV -60 mV -30 mV
2.42 mV
Qap 110 pC
Iclamp 5 nA 6 nA 12 nA
fap 0 Hz 1 Hz 10 Hz
∫
T
ap dtV
0
apap
m
t
restspike
ap CR
R
eVV
Q
apτ
−
−
=
)(
∫
T
ap dtV
0
23. Circuit Design and Simulated Results
• Neuron Emulator Specification and Headstage Circuit
Cell Model with AP Generation
Simplified Model for the Neuron Cell
Simplified AP Generator
• Headstage Amplifiers
Neuron Emulator in C_C
Neuron Emulator in V_C
• Comparison with CV-7B Headstage
CV-7B Headstage in C_C
CV-7B Headstage in V_C
31. Hardware Implementation
• Choice of Components
Microprocessor Programming
• Printed Circuit Board Operation
• Experimental Results
Results of Current Clamp Mode
Results of Voltage Clamp Mode
• Results of Neuron Emulator Mode for CV-7B
Headstage
CV-7B Headstage in C_C
CV-7B Headstage in V_C
• Comparison
32. Printed Circuit Board Opearation
Mode/Switch
C_C
V_C
Current clamp mode
1
0
Voltage clamp mode 0
1
Neuron emulator mode 0
0
15 x 10 cm2
33. Hardware Implementation
• Choice of Components
Microprocessor Programming
• Printed Circuit Board Operation
• Experimental Results
Results of Current Clamp Mode
Results of Voltage Clamp Mode
• Results of Neuron Emulator Mode for CV-7B
Headstage
CV-7B Headstage in C_C
CV-7B Headstage in V_C
• Comparison
34. Results of Current Clamp Mode
Vclamp (CH1), Ve (CH2), φap (CH3)
as the clamp current Iclamp is varied.
Iclamp = 0 nA
-63mV
-30mV
Vpp,Avg=80~90 mV
Vpp,Max=102 mV
35. Results of Voltage Clamp Mode
dtI
R
VV
R
dtCHCH
ap
t
e
clampe
e
t
)(
)21(
0
0
+
−
=
−
= ∫
∫
t
R
VV
e
clampe −
=
ap
t
ap
e
m QdtV
R
tftf ==−→ ∫0
1
1
)()(
Vpp=330mV / 4.4V/V=75mV
f=2.481Hz
400pC / 5=80pC
36. Hardware Implementation
• Choice of Components
Microprocessor Programming
• Printed Circuit Board Operation
• Experimental Results
Results of Current Clamp Mode
Results of Voltage Clamp Mode
• Results of Neuron Emulator Mode for CV-7B
Headstage
CV-7B Headstage in C_C
CV-7B Headstage in V_C
• Comparison
42. Outline
• Introduction
• Objectives & Features
• Circuit Design and Simulated Results
• Hardware Implementation
• Conclusions and Future Work
43. Conclusions and Future Work
• Provide the passive and active electrical propertiespassive and active electrical properties of a neuron as seen
from a single electrode.
• Each AP generates a well defined charge 110 mV,110 mV, ττapap=5ms=5ms. The AP firing
rate from 1 Hz to 10 Hz1 Hz to 10 Hz is dependent on the RP level in the threshold
range from -60 mV to -30 mV-60 mV to -30 mV.
• Measured results confirm the circuit design is in agreement with the
simulation results by Cadence software.
• The headstage circuit is implemented for providing the clamp current to
observe the voltage and current properties of the neuron emulator.
Continue the development of neural oscillator project.
Make the achievements of the thesis realized in a chip (ASIC).
44. Appendix A. Equivalent circuits representing the
function provided by the microcontroller
A1. 2nd
- LPF
A2. VCO
A3. Threshold Comparator
49. A Neuron Emulator and Headstage Circuit
for Patch Clamp Setups
Yen-Cheng Wu
jared76118@gmail.com
Electrical Engineering Department
National Sun Yat-Sen University
Taiwan
Thank you for your attention!Thank you for your attention!
