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Review-CMOS-SIM.pptx

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The document provides an overview of CMOS design concepts including: 1. The structure and operation of CMOS transistors including NMOS and PMOS devices. 2. Basic CMOS gates like the inverter and their voltage transfer characteristics. 3. Effects of device parameters like width, length, voltage and temperature on performance. 4. Other CMOS circuit designs like latches, D-flip flops and transmission gates.

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CONFIDENTIAL Training Review CMOS DESIGN
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Contents CMOS – Structure and operation Others CMOS design CMOS Memory Inverter – the Not logic gate Width/Length – Voltage - Temperature
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation S G D B G D B S p type wafer n-well n+ n+ n+ p+ p+ p+ PMOS NMOS S B G D D G S B NMOS PMOS
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation G G D S B p substrate n+ n+ p+ NMOS G Cross section of an MNOS transistor Thin Oxide (SiO2) Poly (Gate) Length (L) Width (W) W/2 NMOS structure
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation NMOS operation depend on Gate voltage 1. Accumulation 2. Depletion 3. Inversion Accumulation Depletion Inversion Increase VG VT
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation NMOS operation modes 1. Cutoff : VGS < VT 2. Nonsaturation : VGS ≥ VT and VDS ≤ (VGS – VT) 3. Saturation : VGS ≥ VT and VDS ≥ (VGS – VT)     2 2 2 DS DS T gS D V V V V I      2 2 T gS Dsat V V I   
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation NMOS operation modes n+ n+ p- subtrate Vb=0 Depletion electron layer VS=0 0<VT0<VgS VD=0 + + + + + + + + + + + + + + + + + + VS=0 0<VgS<VT0 VD=0 n+ n+ p- subtrate Vb=0 Depletion + + + + + + + + + + + + + + + + + + + + + VS=0 VDS<(VgS-VT0) 0<VT0<VgS n+ n+ p- subtrate Vb=0 Depletion + + + + + + + + + + + + + + + + + + VS=0 0<VT0<VgS L-L L VDS>(VgS-VT0) + + + + + + + + + + + + + + + + + + ID VDS Linear 0 3 T gs V V  Non- Linear Saturation ) (t vDS ) (t iD VDS ID In linear mode, MOS acts like a resistor varying linear with VGS
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation NMOS – V threshole
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation Overlap Capacitors in Mosfet Cols = CoxWLs Cold = CoxWLd
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation 1. Cutoff: no inversion layer channel Gate Capacitors in Mosfet         L W C C C C ox gB gD gS . . 0 0                                 0 1 . . . . 2 1 3 1 . . . . 2 1 , , gB sat ds ds ox gD sat ds ds ox gS C V V L W C C V V L W C C 2. Nonsaturation: 3. Saturation:           0 0 . . . 3 2 gB gD ox gS C C L W C C
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation VgS>0 VDS>0 VgS<0 VDS<0 ID ID NMOS vs PMOS
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation Depletion n-channel Mosfet
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate Ideal Inverter Voltage transfer Characteristic (VTC) Transient response
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate NMOS Inverter structure The load device can be: Linear Resistor Saturated n-Mos Depletion n-Mos Non-saturated n-Mos
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate Inverter with Linear Resistor Load Power dissipate when nMos on
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Vin Vin Rn Rp vdd in out 0v S G D B G D B S NMOS PMOS Vout 0.5vdd R vdd Inverter – the Not logic gate CMOS Inverter
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate Why use CMOS Disdvandtages + Processing is more complex than NMOS + Additional processing for latch-up prevention + CMOS require more transistors than equivalent NMOS-designs Advandtages + CMOS circuits dissipate power only during switching events + VOH = VDD and VOL = 0V + VTC of a CMOS inverter will exhibit a sharp transition
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Latch-up in CMOS p-substrate p+ n+ n+ n-well p+ p+ n+ GND Vdd In Out Vdd GND Out 0 Noise Vdd p+ p+ n p n+ n+ n+ p+ GND Out Rwell Rsub Q1 Q2 Q1 Q2 Rwell Rsub Q2 Q1
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Latch-up Effect Latch-up in CMOS
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL a CMOS circuit G D B S S G D B S G D B VDD A Y VSS G D B S P1 N0 N1 P0 CKB CK VDD A Y VSS Rp0 CKB CK Rp1 Rn1 Rn0 VDD VSS Y A INVZ CK CKB Symbol If [(CK=1)&(CKB=0)] This becomes INV If not [(CK=1)&(CKB=0)] Output is isolated from input, this is called high Z state Others CMOS design CMOS InverterZ
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL a CMOS circuit S P0 VDD D B G N0 G D S B VSS CKB CK IN OUT 0v CL IN OUT Rp Rn CKB CK 0: close 1: close H + 0v CL IN OUT Rp Rn CKB CK 0: close 1: close L + 0 vdd Vin Rp Rn Req Others CMOS design CMOS TGate
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design CMOS TGate
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design Latch Circuit CKB OUT IN TGATE CK VDD VSS VD D VSS Y A INV VSS VDD Y A INV CK CKB Din Dout a CKB OUT IN TGATE CK VDD VSS b Din CK CKB a Dout b Latch a = Din Latch a = Din
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CKB OUT IN TGATE CK VDD VSS VDD VSS Y A INV VSS VDD Y A INV CK CKB Din Dout1 a1 CKB OUT IN TGATE CK VDD VSS b1 CKB OUT IN TGATE CK VDD VSS VDD VSS Y A INV VSS VDD Y A INV Dout2 a2 CKB OUT IN TGATE CK VDD VSS b2 Din CK CKB a1 Dout1 a2 Dout2 Latch Latch Latch Latch
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CK Din Dout1 a1 b1 INV Dout2 a2 b2 Gate1 Gate2 Gate3 Gate4 Gate1,4 Gate2,3 ON ON OFF ON OFF OFF Din  Dout1 Dout1  Dout2 Latch Dout2 Din  Dout1 Latch Dout2 Feed through may occur during this time CK 0 1 0
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CK Din Dout1 a1 b1 INV Dout2 a2 b2 Gate1 Gate2 Gate3 Gate4 Insert buffer to prevent feed through Create internal clock Master stage Slave stage Delay Output buffer An example of DFF circuit
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design Latch - InverterZ
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design Latch - InverterZ
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design DFF InverterZ
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design DFF InverterZ
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL A Y VDD VSS S G D B G D B S G D B S S G D B B N0 N1 P0 P1 Y A B NAND VDD VSS VDD A Y VSS B 1 1 0 Y = A.B Y = 0 only one case: A = 1 and B = 1
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL B Y VDD VSS S G D B G D B S S G D B A N0 N1 P1 P0 G D B S VDD VSS A B Y NOR VDD B Y VSS A 0 0 1 A B Y 0 0 1 0 1 0 1 0 0 1 1 0 Y = A+B Y = 0 if there is any input = 1
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Width/Length – Voltage - Temperature            2 2 1 . DS DS T gS ox n D V V V V L W c I  Design parameter L W Cox n .    Width/Length Wn = 0.2um Wn = 0.1um
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL vdd in out 0v S G D B G D B S NMOS PMOS CL Tp V Tn V PMOS NMOS time Vin Vout ON ON OFF OFF ON ON vdd 0v 0.5vdd Depends on Cin_out and input slew Longer t, higher power consumption ∆𝑡 weaker NMOS stronger NMOS Width/Length – Voltage - Temperature
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL vdd in out 0v S G D B G D B S NMOS PMOS CL Depends on Cin_out and input slew Tp V Tn V PMOS NMOS time Vin Vout ON ON OFF vdd 0v 0.5vdd ON ON OFF weaker PMOS stronger PMOS Longer t, higher power consumption ∆𝑡 Width/Length – Voltage - Temperature
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Vin Vin Rn Rp Vout vdd 0.5vdd R vdd in out 0v S G D B G D B S NMOS PMOS stronger NMOS weaker PMOS Width/Length – Voltage - Temperature
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Vin Vin Rn Rp Vout vdd 0.5vdd R vdd in out 0v S G D B G D B S NMOS PMOS weaker NMOS stronger PMOS Width/Length – Voltage - Temperature
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Vin Vin Rn Rp Vout vdd 0.5vdd R vdd in out 0v S G D B G D B S NMOS PMOS What would a designer expect? A designer would expect Vout = 50% of vdd when Vin = 50% of vdd Width/Length – Voltage - Temperature
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Wn = Wp Wn = 9Wp tpLH tpHL Wp = Wn 4.351ps 1.932ps Wp = 2Wn 4.012ps 2.574ps Wp = 3Wn 3.674ps 3.402ps Wp = 4Wn 3.395ps 4.443ps Effect with Inverter :
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Temperature Green line : 25 0C Yellow line : 120 0C tLH tHL AVG Power -40 oC 10.84ps 12.38ps 117.4 nW 25 oC 12.08ps 12.71ps 191.5 nW 120 oC 13.46ps 13.52ps 448.0 nW_- Effect with Inverter :
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Sweep Temperature, use Transient simulation, measure time delay tLH tHL tpLH tpHL Temp = -4 1.157e-11 1.256e-11 4.408e-12 2.653e-12 Temp = 6 1.175e-11 1.261e-11 4.272e-12 2.616e-12 Temp = 16 1.197e-11 1.267e-11 4.102e-12 2.589e-12 Temp = 26 1.210e-11 1.272e-11 4.001e-12 2.572e-12 Temp = 36 1.225e-11 1.280e-11 3.886e-12 2.556e-12 Temp = 46 1.240e-11 1.287e-11 3.783e-12 2.547e-12 Temp = 56 1.264e-11 1.294e-11 3.690e-12 2.544e-12 Temp = 66 1.269e-11 1.302e-11 3.598e-12 2.543e-12 Temp = 76 1.288e-11 1.310e-11 3.512e-12 2.545e-12 Temp = 86 1.296e-11 1.320e-11 3.438e-12 2.548e-12 Temp = 96 1.308e-11 1.329e-11 3.366e-12 2.553e-12 Temp = 106 1.328e-11 1.339e-11 3.304e-12 2.561e-12
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Sweep Wn, use Transient simulation, measure time delay tLH tHL tpLH tpHL Wn = 0.1 1.063e-11 1.084e-11 4.163e-12 2.810e-12 Wn = 0.2 1.041e-11 1.043e-11 4.639e-12 2.520e-12 Wn = 0.3 1.042e-11 1.010e-11 5.272e-12 2.007e-12 Sweep Vin, use Transient simulation, measure time delay, AVG Power tHL tLH tpHL tpLH Vsup = 0.9Vdd 1.160e-11 1.175e-11 4.340e-12 2.768e-12 Vsup = 0.95Vdd 1.116e-11 1.126e-11 4.258e-12 2.799e-12 Vsup = 1Vdd 1.063e-11 1.084e-11 4.163e-12 2.810e-12 Vsup = 1.05Vdd 1.028e-11 1.046e-11 4.087e-12 2.820e-12 Vsup = 1.1Vdd 9.908e-12 1.008e-11 4.014e-12 2.834e-12 Vsup = 1.15Vdd 9.572e-12 9.822e-12 3.943e-12 2.839e-12
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Fanout Effect deLH deHL Driver 1 Inver 7.593ps 7.857ps Driver 2 Invers 10.37ps 10.58ps
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Memory
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Read Only Memory ROM
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL One column 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1 VDD VDD VDD VDD W3 W2 W1 W0 BL3 BL2 BL1 BL0 Missing contact: Bit 0 Existing contact: Bit 1 One row
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rp Rp Rp Rp 50 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1 VDD VDD VDD VDD W3 W2 W1 W0 BL3 BL2 BL1 BL0
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rp Rp Rp Rp VDD VDD VDD VDD 1 0 0 0 1 0 0 0 VDD VDD VDD 𝑉𝑝 = 𝑅𝑛 𝑅𝑛 + 𝑅𝑝 . 𝑉𝐷𝐷 Rn Rn Rn Rn Rn Rn W3 W2 W1 W0 BL3 BL2 BL1 BL0
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rp Rp Rp Rp VDD VDD VDD VDD 0 1 0 0 0 0 1 0 VDD VDD VDD Rn Rn Rn Rn Rn Rn 𝑉𝑝 W3 W2 W1 W0 BL3 BL2 BL1 BL0
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rn Rn Rp Rp Rp Rp VDD VDD VDD VDD 0 0 1 0 0 1 1 0 VDD VDD Rn Rn Rn Rn 𝑉𝑝 𝑉𝑝 W3 W2 W1 W0 BL3 BL2 BL1 BL0
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rn Rn Rp Rp Rp Rp VDD VDD VDD VDD 0 0 0 1 1 0 0 1 VDD VDD Rn Rn Rn Rn 𝑉𝑝 𝑉𝑝 W3 W2 W1 W0 BL3 BL2 BL1 BL0
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL p substrate n+ n+ S D G SiO2 Poly of main Gate Floating Gate High Voltage Programming Vgsmax (in normal operation mode) Programmed transistor will be OFF always in normal operation mode Only non-programmed transistor can be ON/OFF in normal operation mode This transistor has been programmed, its VT is higher than Vgsmax WL ON OFF Floating Gate MOS (FGMOS) p substrate n+ n+ S D G SiO2 Poly of main Gate Floating Gate
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Erase the data in EPROM p substrate n+ n+ S D G SiO2 Poly of main Gate Floating Gate Apply violet light to the gate to release trapped electrons in the floating gate back to the substrate. This process is used to erase the EPROM before programming new data. p substrate n+ n+ S D G SiO2 Erase the data in EEPROM Floating Gate of FLOTOX MOS, used for EEPROM Apply high voltage to Drain Apply high voltage to the Drain of programmed transistor to release trapped electrons in the floating gate. This process is used to erase the EEPROM before programming new data.
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Static Random Access Memory SRAM
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX WL SRAM cell One column One row 1 0 1 0 Two inverters connected back to back forming a bi-stable circuit, used for storing the data in the cell. Two transistors used for connecting the cell to BL and BLX for writing/ reading operations. They are called pass-gate transistors and they are ON when the word line (WL) is HIGH
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL 0 OFF OFF 1 0 VDD GND 1 0 0 1 0 BL BLX WL 1 VDD GND 1 0 0 0 1 BL BLX WL 1 0 1 Writing [1] into a cell which currently storing [1] Writing [0] into a cell which currently storing [1]
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL 0 OFF OFF 1 0 VDD GND 1 0 0 BL BLX WL 1 GND CBL GND CBLX + + +V 1 1 0 time time WL BL/BLX Reading time Due to large BL/BLX capacitance, if we wait until BL or BLX discharges completely to read the data out, reading time is very long. Sense amplifier is used to reduce reading time  speed up the speed of memory V Turn on the Sense Amplifier to reduce reading time
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL VDD GND 1 0 1 BL BLX WL GND CBL GND CBLX + + +V Vp Vp-V RBL RBLX GND SAEN VDD SAENX YA COLX V 1 1 0 0 0 1 1 V GND CRBL GND CRBLX MEM Core + + Vp Vp-V Vp Vp-V 0 1 Turn on the SA RBL RBLX V Wrong reading
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell . . . . . . . . . . . . . . . . Column 0 Column 1 Column 2 Column n-1 WL0 WL1 WL2 WLm-1 WL Driver
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL . . . . . . . . WLx WL Driver 2 1 3 n 1 2 3 n time Due to long WL  high WL capacitance. If the Driver is not strong enough, the signal at the end of the WL would be not high enough to turn on the cell. An inverter chain with optimum fan-out number is used to minimize the delay. The pulse of WL signal must be long enough to read/write the cell at the and of WL completely. + + + +
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Content Addressable Memory CAM
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL  Content Addressable Memory is a special kind of memory!  Read operation in traditional memory:  Input is address location of the content that we are interested in it.  Output is the content of that address.  In CAM it is the reverse:  Input is associated with something stored in the memory.  Output is location where the associated content is stored. 1 0 1 X X 0 1 1 0 X 0 1 1 X X 1 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 0 1 Content Addressable Memory 1 0 1 X X 0 1 1 0 X 0 1 1 X X 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 X Traditional Memory Address in Data out Search key in Address out
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL  CAM can be used as a search engine.  We want to find matching contents in a database or Table.  Example Routing Table Source: http://pagiamtzis.com/cam/camintro.html
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL  The search-data word is loaded into the search-data register.  All match-lines are pre-charged to high (temporary match state).  Search line drivers broadcast the search word onto the differential search lines.  Each CAM core compares its stored bit against the bit on the corresponding search-lines.  Match-lines that have at least one missing bit, discharge to ground. Source: K. Pagiamtzis, A. Sheikholeslami, “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey,” IEEE J. of Solid-state circuits. March 2006
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CAM Binary CAM (BCAM) Ternary CAM (TCAM) BCAM can only express ‘0’ or ‘1’ (2 values >> need only 1 memory cell ). TCAM can express ‘0’, ‘1’, and ‘X’ (don’t care). (3 value >> need 2 memory cells).
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL MWL CWL HL MWL CWL HL BL BLX HBL HBLX TCAM cell TCAM cell TCAM cell TCAM cell One column One row
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA One TCAM cell BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 1 0 1 Writing data to a TCAM bit-cell is similar to that of SRAM The data is being written into this cell 1 0 VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 1 1 0 The data is being written into this cell 1 0 VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 1 0 1 0 MISS VDD Pre-charge Encoder . . . . . . . . . . . . . MLSA MLSA 1. Pre-charge HL 2. Broadcast the search word onto the differential search lines 3. IF miss, HL will discharge to GND IF match, HL will remain at pre-charge level 4. MLSA detects its ML that has a miss
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 1 0 0 1 MATCH VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA 1. Pre-charge HL 2. Broadcast the search word onto the differential search lines 3. IF miss, HL will discharge to GND IF match, HL will remain at pre-charge level
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 0 1 1 0 MATCH VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 0 1 0 1 MISS VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 0 0 0 1 MATCH ALWAYS VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 0 0 1 0 VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA MATCH ALWAYS
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 1 1 1 0 MISS ALWAYS VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 1 1 0 1 MISS ALWAYS VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Mask-cell Core-cell Compare [0] [1] ML Search bit [1] Storing bit [1] Match Mask-cell Core-cell Compare [1] [0] ML Search bit Storing bit [0] [1] Miss Mask-cell Core-cell Compare [0] [0] ML Search bit Storing bit [X] Match [X] Mask-cell Core-cell Compare [1] [1] ML Search bit [X] Miss We can imagine that a TCAM cell can store bit [0], or bit [1], or bit [X]. The technique is using 2 SRAM cells for those. Each cell must be written independently if they share the same BL/BLX. Don’t use In case a TCAM cell stores bit [X], it matchs always with the data bit. This case is used if we don’t want to compare any specific bit in any search word, and the bit [X] can be stored at any location of the Memory cell array. If we don’t want to compare any specific bit in all search words, bits [X] must be stored in the same column.
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Encoder Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA A1 A0 D2 D1 D0 Search word HBL2 HBL2X HBL1 HBL1X HBL0 HBL0X ML3 ML2 ML1 ML0 Search data register/ driver/ global mask Address out TCAM cell array
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Encoder Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA A1 A0 D2 D1 D0 Search word HBL2 HBL2X HBL1 HBL1X HBL0 HBL0X ML3 (11) ML2 (10) ML1 (01) ML0 (00) Search data register/ driver/ global mask Address out 0 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 The match-line on which all bits match remains in the pre-charged-high state Match-lines that have at least one bit that miss, discharge to GND. High capacitance of ML leads to long discharge time. To speed up the comparison, MLSA is used.
eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Priority Encoder Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA A1 A0 D2 D1 D0 Search word HBL2 HBL2X HBL1 HBL1X HBL0 HBL0X ML3 (11) ML2 (10) ML1 (01) ML0 (00) Search data register/ driver/ global mask Address out 0 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 There could be more than one match-line on which all bits match. In this case, the encoder must be priority encoder type instead of normal encoder. Normally, lower address, higher priority.
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Review-CMOS-SIM.pptx

  • 2. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Contents CMOS – Structure and operation Others CMOS design CMOS Memory Inverter – the Not logic gate Width/Length – Voltage - Temperature
  • 3. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation S G D B G D B S p type wafer n-well n+ n+ n+ p+ p+ p+ PMOS NMOS S B G D D G S B NMOS PMOS
  • 4. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation G G D S B p substrate n+ n+ p+ NMOS G Cross section of an MNOS transistor Thin Oxide (SiO2) Poly (Gate) Length (L) Width (W) W/2 NMOS structure
  • 5. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation NMOS operation depend on Gate voltage 1. Accumulation 2. Depletion 3. Inversion Accumulation Depletion Inversion Increase VG VT
  • 6. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation NMOS operation modes 1. Cutoff : VGS < VT 2. Nonsaturation : VGS ≥ VT and VDS ≤ (VGS – VT) 3. Saturation : VGS ≥ VT and VDS ≥ (VGS – VT)     2 2 2 DS DS T gS D V V V V I      2 2 T gS Dsat V V I   
  • 7. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation NMOS operation modes n+ n+ p- subtrate Vb=0 Depletion electron layer VS=0 0<VT0<VgS VD=0 + + + + + + + + + + + + + + + + + + VS=0 0<VgS<VT0 VD=0 n+ n+ p- subtrate Vb=0 Depletion + + + + + + + + + + + + + + + + + + + + + VS=0 VDS<(VgS-VT0) 0<VT0<VgS n+ n+ p- subtrate Vb=0 Depletion + + + + + + + + + + + + + + + + + + VS=0 0<VT0<VgS L-L L VDS>(VgS-VT0) + + + + + + + + + + + + + + + + + + ID VDS Linear 0 3 T gs V V  Non- Linear Saturation ) (t vDS ) (t iD VDS ID In linear mode, MOS acts like a resistor varying linear with VGS
  • 8. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation NMOS – V threshole
  • 9. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation Overlap Capacitors in Mosfet Cols = CoxWLs Cold = CoxWLd
  • 10. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation 1. Cutoff: no inversion layer channel Gate Capacitors in Mosfet         L W C C C C ox gB gD gS . . 0 0                                 0 1 . . . . 2 1 3 1 . . . . 2 1 , , gB sat ds ds ox gD sat ds ds ox gS C V V L W C C V V L W C C 2. Nonsaturation: 3. Saturation:           0 0 . . . 3 2 gB gD ox gS C C L W C C
  • 11. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation VgS>0 VDS>0 VgS<0 VDS<0 ID ID NMOS vs PMOS
  • 12. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Structure and Operation Depletion n-channel Mosfet
  • 13. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate Ideal Inverter Voltage transfer Characteristic (VTC) Transient response
  • 14. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate
  • 15. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate NMOS Inverter structure The load device can be: Linear Resistor Saturated n-Mos Depletion n-Mos Non-saturated n-Mos
  • 16. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate Inverter with Linear Resistor Load Power dissipate when nMos on
  • 17. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Vin Vin Rn Rp vdd in out 0v S G D B G D B S NMOS PMOS Vout 0.5vdd R vdd Inverter – the Not logic gate CMOS Inverter
  • 18. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate
  • 19. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate
  • 20. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Inverter – the Not logic gate Why use CMOS Disdvandtages + Processing is more complex than NMOS + Additional processing for latch-up prevention + CMOS require more transistors than equivalent NMOS-designs Advandtages + CMOS circuits dissipate power only during switching events + VOH = VDD and VOL = 0V + VTC of a CMOS inverter will exhibit a sharp transition
  • 21. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Latch-up in CMOS p-substrate p+ n+ n+ n-well p+ p+ n+ GND Vdd In Out Vdd GND Out 0 Noise Vdd p+ p+ n p n+ n+ n+ p+ GND Out Rwell Rsub Q1 Q2 Q1 Q2 Rwell Rsub Q2 Q1
  • 22. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Latch-up Effect Latch-up in CMOS
  • 23. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL a CMOS circuit G D B S S G D B S G D B VDD A Y VSS G D B S P1 N0 N1 P0 CKB CK VDD A Y VSS Rp0 CKB CK Rp1 Rn1 Rn0 VDD VSS Y A INVZ CK CKB Symbol If [(CK=1)&(CKB=0)] This becomes INV If not [(CK=1)&(CKB=0)] Output is isolated from input, this is called high Z state Others CMOS design CMOS InverterZ
  • 24. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL a CMOS circuit S P0 VDD D B G N0 G D S B VSS CKB CK IN OUT 0v CL IN OUT Rp Rn CKB CK 0: close 1: close H + 0v CL IN OUT Rp Rn CKB CK 0: close 1: close L + 0 vdd Vin Rp Rn Req Others CMOS design CMOS TGate
  • 25. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design CMOS TGate
  • 26. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design Latch Circuit CKB OUT IN TGATE CK VDD VSS VD D VSS Y A INV VSS VDD Y A INV CK CKB Din Dout a CKB OUT IN TGATE CK VDD VSS b Din CK CKB a Dout b Latch a = Din Latch a = Din
  • 27. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CKB OUT IN TGATE CK VDD VSS VDD VSS Y A INV VSS VDD Y A INV CK CKB Din Dout1 a1 CKB OUT IN TGATE CK VDD VSS b1 CKB OUT IN TGATE CK VDD VSS VDD VSS Y A INV VSS VDD Y A INV Dout2 a2 CKB OUT IN TGATE CK VDD VSS b2 Din CK CKB a1 Dout1 a2 Dout2 Latch Latch Latch Latch
  • 28. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CK Din Dout1 a1 b1 INV Dout2 a2 b2 Gate1 Gate2 Gate3 Gate4 Gate1,4 Gate2,3 ON ON OFF ON OFF OFF Din  Dout1 Dout1  Dout2 Latch Dout2 Din  Dout1 Latch Dout2 Feed through may occur during this time CK 0 1 0
  • 29. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CK Din Dout1 a1 b1 INV Dout2 a2 b2 Gate1 Gate2 Gate3 Gate4 Insert buffer to prevent feed through Create internal clock Master stage Slave stage Delay Output buffer An example of DFF circuit
  • 30. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design Latch - InverterZ
  • 31. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design Latch - InverterZ
  • 32. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design DFF InverterZ
  • 33. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Others CMOS design DFF InverterZ
  • 34. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL A Y VDD VSS S G D B G D B S G D B S S G D B B N0 N1 P0 P1 Y A B NAND VDD VSS VDD A Y VSS B 1 1 0 Y = A.B Y = 0 only one case: A = 1 and B = 1
  • 35. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL B Y VDD VSS S G D B G D B S S G D B A N0 N1 P1 P0 G D B S VDD VSS A B Y NOR VDD B Y VSS A 0 0 1 A B Y 0 0 1 0 1 0 1 0 0 1 1 0 Y = A+B Y = 0 if there is any input = 1
  • 36. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Width/Length – Voltage - Temperature            2 2 1 . DS DS T gS ox n D V V V V L W c I  Design parameter L W Cox n .    Width/Length Wn = 0.2um Wn = 0.1um
  • 37. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL vdd in out 0v S G D B G D B S NMOS PMOS CL Tp V Tn V PMOS NMOS time Vin Vout ON ON OFF OFF ON ON vdd 0v 0.5vdd Depends on Cin_out and input slew Longer t, higher power consumption ∆𝑡 weaker NMOS stronger NMOS Width/Length – Voltage - Temperature
  • 38. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL vdd in out 0v S G D B G D B S NMOS PMOS CL Depends on Cin_out and input slew Tp V Tn V PMOS NMOS time Vin Vout ON ON OFF vdd 0v 0.5vdd ON ON OFF weaker PMOS stronger PMOS Longer t, higher power consumption ∆𝑡 Width/Length – Voltage - Temperature
  • 39. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Vin Vin Rn Rp Vout vdd 0.5vdd R vdd in out 0v S G D B G D B S NMOS PMOS stronger NMOS weaker PMOS Width/Length – Voltage - Temperature
  • 40. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Vin Vin Rn Rp Vout vdd 0.5vdd R vdd in out 0v S G D B G D B S NMOS PMOS weaker NMOS stronger PMOS Width/Length – Voltage - Temperature
  • 41. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Vin Vin Rn Rp Vout vdd 0.5vdd R vdd in out 0v S G D B G D B S NMOS PMOS What would a designer expect? A designer would expect Vout = 50% of vdd when Vin = 50% of vdd Width/Length – Voltage - Temperature
  • 42. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Wn = Wp Wn = 9Wp tpLH tpHL Wp = Wn 4.351ps 1.932ps Wp = 2Wn 4.012ps 2.574ps Wp = 3Wn 3.674ps 3.402ps Wp = 4Wn 3.395ps 4.443ps Effect with Inverter :
  • 43. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Temperature Green line : 25 0C Yellow line : 120 0C tLH tHL AVG Power -40 oC 10.84ps 12.38ps 117.4 nW 25 oC 12.08ps 12.71ps 191.5 nW 120 oC 13.46ps 13.52ps 448.0 nW_- Effect with Inverter :
  • 44. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Sweep Temperature, use Transient simulation, measure time delay tLH tHL tpLH tpHL Temp = -4 1.157e-11 1.256e-11 4.408e-12 2.653e-12 Temp = 6 1.175e-11 1.261e-11 4.272e-12 2.616e-12 Temp = 16 1.197e-11 1.267e-11 4.102e-12 2.589e-12 Temp = 26 1.210e-11 1.272e-11 4.001e-12 2.572e-12 Temp = 36 1.225e-11 1.280e-11 3.886e-12 2.556e-12 Temp = 46 1.240e-11 1.287e-11 3.783e-12 2.547e-12 Temp = 56 1.264e-11 1.294e-11 3.690e-12 2.544e-12 Temp = 66 1.269e-11 1.302e-11 3.598e-12 2.543e-12 Temp = 76 1.288e-11 1.310e-11 3.512e-12 2.545e-12 Temp = 86 1.296e-11 1.320e-11 3.438e-12 2.548e-12 Temp = 96 1.308e-11 1.329e-11 3.366e-12 2.553e-12 Temp = 106 1.328e-11 1.339e-11 3.304e-12 2.561e-12
  • 45. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Sweep Wn, use Transient simulation, measure time delay tLH tHL tpLH tpHL Wn = 0.1 1.063e-11 1.084e-11 4.163e-12 2.810e-12 Wn = 0.2 1.041e-11 1.043e-11 4.639e-12 2.520e-12 Wn = 0.3 1.042e-11 1.010e-11 5.272e-12 2.007e-12 Sweep Vin, use Transient simulation, measure time delay, AVG Power tHL tLH tpHL tpLH Vsup = 0.9Vdd 1.160e-11 1.175e-11 4.340e-12 2.768e-12 Vsup = 0.95Vdd 1.116e-11 1.126e-11 4.258e-12 2.799e-12 Vsup = 1Vdd 1.063e-11 1.084e-11 4.163e-12 2.810e-12 Vsup = 1.05Vdd 1.028e-11 1.046e-11 4.087e-12 2.820e-12 Vsup = 1.1Vdd 9.908e-12 1.008e-11 4.014e-12 2.834e-12 Vsup = 1.15Vdd 9.572e-12 9.822e-12 3.943e-12 2.839e-12
  • 46. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Width/Length – Voltage - Temperature Fanout Effect deLH deHL Driver 1 Inver 7.593ps 7.857ps Driver 2 Invers 10.37ps 10.58ps
  • 47. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CMOS Memory
  • 48. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Read Only Memory ROM
  • 49. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL One column 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1 VDD VDD VDD VDD W3 W2 W1 W0 BL3 BL2 BL1 BL0 Missing contact: Bit 0 Existing contact: Bit 1 One row
  • 50. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rp Rp Rp Rp 50 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1 VDD VDD VDD VDD W3 W2 W1 W0 BL3 BL2 BL1 BL0
  • 51. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rp Rp Rp Rp VDD VDD VDD VDD 1 0 0 0 1 0 0 0 VDD VDD VDD 𝑉𝑝 = 𝑅𝑛 𝑅𝑛 + 𝑅𝑝 . 𝑉𝐷𝐷 Rn Rn Rn Rn Rn Rn W3 W2 W1 W0 BL3 BL2 BL1 BL0
  • 52. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rp Rp Rp Rp VDD VDD VDD VDD 0 1 0 0 0 0 1 0 VDD VDD VDD Rn Rn Rn Rn Rn Rn 𝑉𝑝 W3 W2 W1 W0 BL3 BL2 BL1 BL0
  • 53. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rn Rn Rp Rp Rp Rp VDD VDD VDD VDD 0 0 1 0 0 1 1 0 VDD VDD Rn Rn Rn Rn 𝑉𝑝 𝑉𝑝 W3 W2 W1 W0 BL3 BL2 BL1 BL0
  • 54. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Rn Rn Rp Rp Rp Rp VDD VDD VDD VDD 0 0 0 1 1 0 0 1 VDD VDD Rn Rn Rn Rn 𝑉𝑝 𝑉𝑝 W3 W2 W1 W0 BL3 BL2 BL1 BL0
  • 55. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL p substrate n+ n+ S D G SiO2 Poly of main Gate Floating Gate High Voltage Programming Vgsmax (in normal operation mode) Programmed transistor will be OFF always in normal operation mode Only non-programmed transistor can be ON/OFF in normal operation mode This transistor has been programmed, its VT is higher than Vgsmax WL ON OFF Floating Gate MOS (FGMOS) p substrate n+ n+ S D G SiO2 Poly of main Gate Floating Gate
  • 56. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Erase the data in EPROM p substrate n+ n+ S D G SiO2 Poly of main Gate Floating Gate Apply violet light to the gate to release trapped electrons in the floating gate back to the substrate. This process is used to erase the EPROM before programming new data. p substrate n+ n+ S D G SiO2 Erase the data in EEPROM Floating Gate of FLOTOX MOS, used for EEPROM Apply high voltage to Drain Apply high voltage to the Drain of programmed transistor to release trapped electrons in the floating gate. This process is used to erase the EEPROM before programming new data.
  • 57. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Static Random Access Memory SRAM
  • 58. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX WL SRAM cell One column One row 1 0 1 0 Two inverters connected back to back forming a bi-stable circuit, used for storing the data in the cell. Two transistors used for connecting the cell to BL and BLX for writing/ reading operations. They are called pass-gate transistors and they are ON when the word line (WL) is HIGH
  • 59. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL 0 OFF OFF 1 0 VDD GND 1 0 0 1 0 BL BLX WL 1 VDD GND 1 0 0 0 1 BL BLX WL 1 0 1 Writing [1] into a cell which currently storing [1] Writing [0] into a cell which currently storing [1]
  • 60. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL 0 OFF OFF 1 0 VDD GND 1 0 0 BL BLX WL 1 GND CBL GND CBLX + + +V 1 1 0 time time WL BL/BLX Reading time Due to large BL/BLX capacitance, if we wait until BL or BLX discharges completely to read the data out, reading time is very long. Sense amplifier is used to reduce reading time  speed up the speed of memory V Turn on the Sense Amplifier to reduce reading time
  • 61. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL VDD GND 1 0 1 BL BLX WL GND CBL GND CBLX + + +V Vp Vp-V RBL RBLX GND SAEN VDD SAENX YA COLX V 1 1 0 0 0 1 1 V GND CRBL GND CRBLX MEM Core + + Vp Vp-V Vp Vp-V 0 1 Turn on the SA RBL RBLX V Wrong reading
  • 62. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell . . . . . . . . . . . . . . . . Column 0 Column 1 Column 2 Column n-1 WL0 WL1 WL2 WLm-1 WL Driver
  • 63. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL . . . . . . . . WLx WL Driver 2 1 3 n 1 2 3 n time Due to long WL  high WL capacitance. If the Driver is not strong enough, the signal at the end of the WL would be not high enough to turn on the cell. An inverter chain with optimum fan-out number is used to minimize the delay. The pulse of WL signal must be long enough to read/write the cell at the and of WL completely. + + + +
  • 64. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Content Addressable Memory CAM
  • 65. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL  Content Addressable Memory is a special kind of memory!  Read operation in traditional memory:  Input is address location of the content that we are interested in it.  Output is the content of that address.  In CAM it is the reverse:  Input is associated with something stored in the memory.  Output is location where the associated content is stored. 1 0 1 X X 0 1 1 0 X 0 1 1 X X 1 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 0 1 Content Addressable Memory 1 0 1 X X 0 1 1 0 X 0 1 1 X X 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 X Traditional Memory Address in Data out Search key in Address out
  • 66. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL  CAM can be used as a search engine.  We want to find matching contents in a database or Table.  Example Routing Table Source: http://pagiamtzis.com/cam/camintro.html
  • 67. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL
  • 68. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL
  • 69. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL  The search-data word is loaded into the search-data register.  All match-lines are pre-charged to high (temporary match state).  Search line drivers broadcast the search word onto the differential search lines.  Each CAM core compares its stored bit against the bit on the corresponding search-lines.  Match-lines that have at least one missing bit, discharge to ground. Source: K. Pagiamtzis, A. Sheikholeslami, “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey,” IEEE J. of Solid-state circuits. March 2006
  • 70. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL CAM Binary CAM (BCAM) Ternary CAM (TCAM) BCAM can only express ‘0’ or ‘1’ (2 values >> need only 1 memory cell ). TCAM can express ‘0’, ‘1’, and ‘X’ (don’t care). (3 value >> need 2 memory cells).
  • 71. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL MWL CWL HL MWL CWL HL BL BLX HBL HBLX TCAM cell TCAM cell TCAM cell TCAM cell One column One row
  • 72. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA One TCAM cell BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL
  • 73. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 1 0 1 Writing data to a TCAM bit-cell is similar to that of SRAM The data is being written into this cell 1 0 VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
  • 74. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 1 1 0 The data is being written into this cell 1 0 VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
  • 75. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 1 0 1 0 MISS VDD Pre-charge Encoder . . . . . . . . . . . . . MLSA MLSA 1. Pre-charge HL 2. Broadcast the search word onto the differential search lines 3. IF miss, HL will discharge to GND IF match, HL will remain at pre-charge level 4. MLSA detects its ML that has a miss
  • 76. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 1 0 0 1 MATCH VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA 1. Pre-charge HL 2. Broadcast the search word onto the differential search lines 3. IF miss, HL will discharge to GND IF match, HL will remain at pre-charge level
  • 77. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 0 1 1 0 MATCH VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
  • 78. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 0 1 0 1 MISS VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
  • 79. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 0 0 0 1 MATCH ALWAYS VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
  • 80. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 0 0 1 0 VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA MATCH ALWAYS
  • 81. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 1 1 1 0 MISS ALWAYS VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
  • 82. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL BL BLX MWL GND ICBL ICBLX IMBL IMBLX HBL HBLX CWL HL 0 0 1 1 0 1 MISS ALWAYS VDD Pre-charge Encoder . . . . . . . . . . . . . . MLSA MLSA
  • 83. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Mask-cell Core-cell Compare [0] [1] ML Search bit [1] Storing bit [1] Match Mask-cell Core-cell Compare [1] [0] ML Search bit Storing bit [0] [1] Miss Mask-cell Core-cell Compare [0] [0] ML Search bit Storing bit [X] Match [X] Mask-cell Core-cell Compare [1] [1] ML Search bit [X] Miss We can imagine that a TCAM cell can store bit [0], or bit [1], or bit [X]. The technique is using 2 SRAM cells for those. Each cell must be written independently if they share the same BL/BLX. Don’t use In case a TCAM cell stores bit [X], it matchs always with the data bit. This case is used if we don’t want to compare any specific bit in any search word, and the bit [X] can be stored at any location of the Memory cell array. If we don’t want to compare any specific bit in all search words, bits [X] must be stored in the same column.
  • 84. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Encoder Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA A1 A0 D2 D1 D0 Search word HBL2 HBL2X HBL1 HBL1X HBL0 HBL0X ML3 ML2 ML1 ML0 Search data register/ driver/ global mask Address out TCAM cell array
  • 85. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Encoder Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA A1 A0 D2 D1 D0 Search word HBL2 HBL2X HBL1 HBL1X HBL0 HBL0X ML3 (11) ML2 (10) ML1 (01) ML0 (00) Search data register/ driver/ global mask Address out 0 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 The match-line on which all bits match remains in the pre-charged-high state Match-lines that have at least one bit that miss, discharge to GND. High capacitance of ML leads to long discharge time. To speed up the comparison, MLSA is used.
  • 86. eSilicon • Enabling Your Silicon Success™ CONFIDENTIAL Priority Encoder Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA Pre-charge VDD MLSA A1 A0 D2 D1 D0 Search word HBL2 HBL2X HBL1 HBL1X HBL0 HBL0X ML3 (11) ML2 (10) ML1 (01) ML0 (00) Search data register/ driver/ global mask Address out 0 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 There could be more than one match-line on which all bits match. In this case, the encoder must be priority encoder type instead of normal encoder. Normally, lower address, higher priority.