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1. EE5111
Micro-Electronics and Device
Simulation LAB
MOS - CAPACITOR
FABRICATION AND CHARACTERISATION
ee16mtech11012 (Shinde A)

2. Contents
1. Objective
2. Fabrication Process
3 . Experiment Results
4. TCAD simulations
5. Conclusion

3. • Objective
To fabricate a MOS Capacitor and to obtain C-V characteristics .

4. 3. Fabrication Process
• Wafer Cleaning
The wafer cleaning steps –
1) DI – De Ionized water dip of silicon wafer
2) RCA-1
Solution composed of 1:1:5 of NH4OH:H2O2: DI water is heated up
to 750 C.
3) DI water dip
4) HF dip
5) DI water dip
6) RCA-2

5. 7) RCA-2
Solution composed of 1:1:5 of HCl : H2O2: DI water is heated up
to 750 C.
8) DI water dip
9) HF dip
10) DI water dip
11) Wafer is dried using Compressed Dry Air (CDA)

6. Oxidation
Procedure followed:
a. The wafers are fed to the furnace in a quartz boat.
b. Temperature is ramped up to 8500 C.
c. Oxygen is supplied to the chamber.
d. Oxygen supply is cut down.
e. Temperature is ramped down.
f. Wafers are unloaded.

7. 3. Patterning - Etching
• The oxidized silicon wafer is spin coated with positive photoresist.
• Spin-coated wafer is de-hydrated (100oC) and then Baked wafer is
undergone through lithography.
• The soluble photoresist exposed in lithography.
• Etched using Dilute Hydrofluoric Acid (DHF) solution to remove the
oxide layer.

8. Metallization
• Here Gold is used as metal and the thickness was 100nm deposited
through Electron Gun Evaporation.

9. Lithography
• It is the last step of MOS cap fabrication.
• LASER writing is used here for patterning on the wafer.
• After metallization, wafer is spin coated with photoresist.
• Dehydration bake is done after spin coating in the end.

10. 1. Mos Capacitor – CV Characterisation

11. TCAD SIMULATIONS
• 2-D DG n-MOSFET using Sentaurus SDE
A.Doping information

12. B. Structure after meshing

13. Objective 1: Linear and Saturated transfer characteristics (both in linear
and log scale). Extract ION, IOFF, VthLin, VthSat, DIBL, SS, Max gin.
• Linear mode: VDS = 100 mV; VGS varied from (0-1) V:

14. • Saturation mode: VDS = 1 V; VGS varied from (0-1) V:

15. Ion & Ioff :
Measured Ion value: 2.7 mA
Measured Ioff value: 3.7286nA

16. Vth Linear:-
Measured Value:- 170mV

17. Vth Saturation:
Measured Value:- 130mV

18. Subthreshold swing:
Measured Value: 72.6 mV/decade

19. Maximum Gm:
Measured Value: 42.9 m Siemens

20. Objective 2: Output characteristics for VGS = 0.2 V, 0.4 V, 0.6 V, 0.8 V, 1 V. Extract VDsat
and GD
VGS(V) VDsat(V)
0.2 0.044529
0.4 0.082067
0.6 0.112842
0.8 0.136342
1 0.161858

21. ID Vs VDS:

22. GD vs VDS:

23. Objective 3: Plot the 1- D Drain electric field, drift velocity, and
conduction band edge profile along the channel at VGS = 1 V, and VDS =
1 V.
• Drift Velocity v1: 3.9e+8 cm/s v2: 3.6e+8 cm/s

24. Conduction band edge:-

25. Objective 4: Plot the 1-D quantum mechanical inversion charge density
across and along the channel at VGS — Vth = 0.2 V.

26. Objective 5: Plot the simulated 2-D color map plots of quantum
corrected inversion charge density in the device active region at VGS –
Vth = 0.2 V.
• Classical

27. b. Quantum corrected

28. CONCLUSION :-
• Therefore we have successfully completed Mos Capacitor Fabrication
And Characterisation. We had simulated DGMOS in TCAD and verified
characteristics like I-V, electron densities, electric field etc.