Doubling the clock rate - doubles the number of transistors - increasing the power dissipation, and the Scaling paradigm is going to stop at some point. To overcome this performance gap, device physics need to be researched.

1. Seminar on
Ferroelectric FET’s Based
Non-volatile Logic-in-Memory Circuits
Guided By,
Prof. Dr. Cheeran
Prepared by,
Siddhi Kadam
182081014
Sem I, M.Tech.(Electronics)
1

2. Contents
• Objective
• Literature Survey
• What are Ferroelectric FET’s
 Sub-threshold Slope
 Negative Capacitance
 Static Power dissipation
• FeFET as a switch and a non-volatile memory element
 Hysteresis
 FRAM
2

3. Contents
• PiM vs. LiM
• Logic-in-Memory
 RAM vs. CAM vs. TCAM
• Comparison between CMOS, ReRam, MTJs and FeFET based
LiM’s (TCAM)
• Conclusion
• References
3

4. Objective [6]
4

5. • Clock frequency is stuck at 3Ghz
• Doubling the clock rate – doubles the number of transistors –
doubles the power dissipation
• To overcome this: Transistors and voltages can be scaled –
but scaling leads to leakage currents – SCALING PARADIGM
IS GOING TO STOP
• So, to continue the performance gain: Physics of the device
need to be studied
5

6. Literature survey
Paper 1 Xunzhao Yin , Student Member, IEEE, Xiaoming Chen
, Member, IEEE, Michael Niemier, Senior Member,
IEEE, and Xiaobo Sharon Hu , Fellow, IEEE,
“Ferroelectric FETs based non-volatile Logic-in-
memory circuits”, IEEE Transaction on VLSI, 2019
Introduction In this paper, the authors have exploited the FeFET property
that allows a device to function as both, a switch and a non-
volatile memory element. Thereby, using this property to build
a LiM circuit and have compared FeFET based LiM’s with
other technologies.
6

7. Paper 2 Cheng-I Lin, Asif Islam Khan, Member, IEEE,
Sayeef Salahuddin, Senior Member, IEEE,
and Chenming Hu, Fellow, IEEE, “Effects of the
Variation of Ferroelectric Properties
on Negative Capacitance FET Characteristics”,
IEEE Transaction on Electronic Devices, 2016
Introduction In this paper, the authors have studied the effects of the
variation of ferroelectric material properties (thickness,
polarization etc.) on the performance of negative
capacitance FETs (NCFETs).
7

8. Ferroelectric FET’s
SUB-THRESHOLD SLOPE [7]
Conventional Novel FET
MOSFET
8

9. Ferroelectric FET’s
NEGATIVE CAPACITANCE [2,5]
• Replace oxide with a material
that has a negative capacitance
• Cins < zero: A smaller change
in gate voltage creates larger
change in intermediate
voltage – VOLTAGE
AMPLIFICATION
9

10. NEGATIVE CAPACITANCE (contd.)
10

11. Ferroelectric FET’s
STATIC POWER DISSIPATION [4]
11

12. FeFET as a switch and a non-
volatile memory element
• As a SWITCH [1,5]:
12

13. As a NON-VOLATILE MEMORY element [8]:
Ferroelectric vs. Dielectric: Ferroelectric possess
Polarization even in the absence of Electric field –
SPONTANEOUS POLARIZATION
There are pre-existing dipoles in this ferroelectric material
They originate from minor deviation from crystallographic
symmetry
13

14. BaTiO3–Important component
of perovskite family of ferroelectric
14

15. • Hysteresis [8]
15

16. FRAM – NON-VOLATILE RAM [9]
• Speed - 1000x faster then Flash and EEPROM
• Low Power - 1.5v compared to 10-14v for Flash
• Reliability - retains its data for more than 10 years at 85
degrees C, or 100 years at 25C
• Not affected by magnetic fields
16

17. 17

18. PiM vs. LiM [1,3]
58W of a 65W power budget would be allocated to just
data transfer.
18

19. PiM vs. LiM – contd.
19

20. LiM – RAM vs. CAM vs. TCAM
• RAM vs. CAM
20

21. TCAM
21

22. Comparison between CMOS,
ReRam, MTJs and FeFET based
LiM’s (TCAM) [1]
22

23. Comparison -contd
CMOS ReRAM MTJ
Area
overhead
42% less - 79% less
EDP 1.3x 1.7x 149x
23

24. Conclusion
• FeFET based NV circuits are faster compared to other NV
circuits.
• They are very low-power devices.
• Data reliability is high.
• Flash based memory takes more time to erase the data,
FRAM’s uses symmetrical read/write time.
• Though they are faster than Flash/EEPROM, but are
costlier to implement.
24

25. References
1) Xunzhao Yin, Xiaoming Chen, Michael Niemier, and Xiaobo
Sharon Hu, “FETs-Based Nonvolatile Logic-in-
Memory Circuits”, ieee transactions on very large scale
integration (vlsi) systems, 2019
2) Cheng-I Lin, Asif Islam Khan, Sayeef Salahuddin, and
Chenming Hu, “Effects of the Variation of
Ferroelectric Properties on Negative Capacitance
FET Characteristics”, ieee transactions on electron
devices, 2016
25

26. 3) Gagandeep Singh, Lorenzo Chelini, Stefano Corda, Ahsan
Javed Awan, Sander Stuijk, Roel Jordans, Henk Corporaal,
Albert-Jan Boonstra, 2018 21st Euromicro Conference on
Digital System Design, “A Review of Near-Memory
Computing Architectures: Opportunities and
Challenges”
4) Sayeef Salahuddin and Supriyo Datta, “Use of Negative
Capacitance to Provide Voltage Amplification for
Low Power Nanoscale Devices”, Nanoletters, 2008
26

27. 5) Sayeef Salahuddin and Supriyo Datta, “Use of Negative
Capacitance to Provide Voltage Amplification for Low
Power Nanoscale Devices”, Nanoletters, 2008
6)http://digitalassets.lib.berkeley.edu/etd/ucb/text/Khanberke
ley_0028E_15440.pdf-Negative Capacitance for Ultra-low
Power Computing by Asif Islam Khan
7)https://www.youtube.com/watch?v=sygP7ZzTAM4 -
Negative Capacitance Technology for Ultra-low Power
Computing - Asif Khan
27

28. 8)https://www.youtube.com/watch?v=qXLStQQxHzU – Mod-
08 Lec-19 Ferroelectric , Piezoelectric and Pyroelectric Ceramics
9)http://www.ti.com/lit/ml/slat151/slat151.pdf - FRAM FAQs
Texas Instruments
10)https://www.youtube.com/watch?v=hQMRMvXjjHE-
FRAM Write Speed Demo (FRAM vs. SRAM vs. EEPROM)
11) https://slideplayer.com/slide/8768734/ - RAM vs CAM vs
TCAM
28

29. THANK YOU
29