VHDL IMPLEMENTATION OF ENCRYPTION MODULE OF AES

1. VHDL IMPLEMENTATION
OF ENCRYPTION MODULE OF AES
Synopsis
for
Final year project of
B.Tech.
In
Electronics &Communication Engineering
Submitted to
Raj Kumar Goel Institute Of Technology, Ghaziabad
Under the guidance of:
KUNAL LALA
(Asst. Prof ,ECE Dept.)
Name of the Scholars
SHUBHAM CHAUHAN +918285856742
ROSHNI AWASTHI +919911917127
JAYANT YADAV +919911906063
GROUP NO…………….

2. CONTENTS
 ABSTRACT
 INTRODUCTION
 DIFFERENT MODULES OF AES ALGORITHM
 SOFTWARE & LANGUAGE USED
 PLANNING AND METHODOLOGY OF WORK

3. ABSTRACT
Security has become an increasingly important feature with the growth of electronic
communication. The Symmetric, or secret key algorithms, a cryptography method in
which the same key value is used in both the encryption and decryption calculations
are becoming more popular. The keys, in practice, represent a shared secret between
two or more users that can be used to maintain a private information link. Secret key
cryptography uses conventional algorithm that is Advanced Encryption Standard
(AES) algorithm. The AES algorithm is capable of using cryptographic keys of 128,
192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. This standard is
based on the RIJNDEAL algorithm. All the modules are compared with different
families of FPGA platforms. This methodology uses VHDL implementation the
modules in terms of Delay and Frequency.

4. INTRODUCTION
Nowadays cryptography has a main role in embedded systems design. In many
applications, the data requires a secured connection which is usually achieved by
cryptography. Cryptography is divided in two categories first is symmetric key
cryptography (sender and receiver shares the same key) and the second one is
asymmetric key cryptography. Here we are concerned about symmetric key
cryptography due to its use in military application, embedded system design, financial
and legal files, medical reports, and bank services via Internet, telephone
conversations, and e-commerce transactions etc. Many symmetric key cryptographic
algorithms were proposed, such as the Data Encryption Standard (DES), the Elliptic
Curve Cryptography (ECC), the Advanced Encryption Standard (AES) and other
algorithms. Here the hardware implementation of AES algorithm is presented to
increase the data transfer speed. Objective of the dissertation is to perform an efficient
method of implementing a AES algorithm with minimum delay and having high
performance in terms of delay while maintaining the proper functionality of the
system. The software used for the implementation of the algorithm is Xilinx 6.1 and
language used is VHDL (very high speed integrated circuit hardware description
language). Simulation of encryption process of the AES algorithm has been done
using the Xilinx software. Inputs will be converted into binary form and given as input
to the "Model-Sim Simulator" of XILINX.

5. DIFFERENT MODULE OF AES ALGORITHMS
The Data processing unit have four main modules or transformations in which
sub byte transform, shift rows, mix column and add round key are involved and
the Key Expansion unit generate the round key for the next round.
1. SUB BYTE TRANSFORM :-A byte-by-byte substitution during the forward
process .The corresponding substitution step used during decryption is called
INV Sub Bytes. This step consists of using a 16 × 16 lookup table to find
replacement byte for a given byte in the input state array. The entries in the
lookup table are created by using the notions of multiplicative inverses in GF
(2^8 ) and bit scrambling to destroy the bit-level correlations inside each byte.
2. SHIFT ROW TRANSFORM :-Cyclic shifts the rows of the State over
different offsets. The operation is almost the same in the decryption process
except for the fact that the shifting offsets have different values [2]. The goal of
this transformation is to scramble the byte order inside each 128-bit block.
3. MIX COLUMN TRANSFORM :-This process is for mixing up of the bytes in
each column separately during the forward process. The corresponding
transformation during decryption is denoted INV Mix Columns and stands for
inverse mix column transformation. The goal is here is to further scramble up
the 128-bit input block.
4. ADD ROUND KEY AND KEY EXPANSION:- In this operation, the round
key is applied to the State by simple bit by bit XOR. Basically Key Expansion
unit is used to generate the next round key as for three different key size, AES
consist of 10, 12 or 14 rounds. So after every round a new round key need to be
produced. So this unit produces that round key for each round. This unit also
utilize the concept of shifting the bytes and substitution of bytes which were
used in Data processing unit.The whole encryption unit is shown in Figure.

6. Figure. Encryption Module of AES

7. PLANNING & METHODOLOGY
 We have taken this project as it is mostly used nowadays and have a good
scope in future .
 We have planned to divide the work into sub groups and we decided to
complete theoretical part by the month December before the starting of
semester exams.
 We have already started our research work and land up to certain good results.
We need little more time to go through the topic thoroughly.
 And the practical implementation of the VHDL implementation is to be shown
in the next semester as the major project.