Implementation of photonics in Arithmetic Logic Unit (ALU)

1. Electronic-photonic Arithmetic Logic
Unit For
High-Speed Computing
Shreyan Datta

2. The most important component of a Arithmetic Logic Unit
(ALU) is the Full Adder Circuit, In this presentation we
discuss the type of the full adder used and how the electro-
photonic adaptation of the same enhances the ALU in
what aspects.

3. FULL ADDER
Propagation Unit Generation Unit
Pn=An⊕Bn Gn=An.Bn

4. Pn=An⊕Bn, Gn=An.Bn
Cn= C(n-1).Pn+Gn
Sn= Cn⊕Pn

5. The adder used is a type of Carry Select Adder where we
break the N-Bit Full Adder Circuit into n sets of m-bit full
adders. (N=mxn)
Simultaneous calculation in n sets of full adders reduces the
overall latency of the Full Adder.
Characteristic of the Full Adder Circuit

6. Schematic of a Ripple Carry Adder Schematic of a Carry Select Adder

7. General architecture of the WDM-based EPALU, consisting of a (p, g) generation unit (PGU), n sets of m-bit
optical carry propagation networks (OCPNs) and an array of fast photodetectors (PDs) along with a network of
electronic multiplexer units (MUXU) and
an electronic sum generation unit (SGU).

8. The Inputs to the Optical Carry Propagation Network (OCPN) are two different
wavelengths with 0 and 1 encoded on them sent through a single OCPN thus
reducing the latency of the system
There are electro-optic modulators and couplers that are used to modulate the
CW lasers according to the Propagation and Generation Unit inputs.
The output carry for m-bit full adder, for both 1 and 0 as input carry are always
ready and only the required output is extracted once the actual input carry is
know and accordingly fed to the MUX.

9. The Optical Carry Propagation Network

10. Structure of 1-bit in OCPN

11. Multiplexer Design
A conventional tree type MUX is used in the MUX design. The photon
assisted MUX in the EPALU needs only one set of hardware as
compared to the electronic ALU.

12. MUX Design used in the EPALU

13. Circuit diagram of the PGU and SGU
Circuit diagram of the PGU and SGU. a) Schematic of the (p, g)
generation unit, consisting of XOR gates and OR gates.
b) Schematic of the sum generation unit, consisting of XOR gates.

14. Effect on Computation Speeds
● The proposed EPALU is promising to escape the
effects of heat (heat death) thus go beyond the
computation speed limits.
● The highly scaled micro-size optical components also
enable the light to process information in sub-
picoseconds which is 1–2 orders of magnitude faster
than electrical gates, leading to a much higher
operating speed of the entire circuits

15. Estimations
The power estimations were done based on the state of the art photonic components.
The waveguide propagation loss is 0.002 dB/bit (1 dB/cm)
The insertion loss of directional coupler is 0.05 dB
The insertion loss of grating/edge coupler is 1 dB
The insertion loss of modulator is 0.5 dB
Input coupler loss= 1dB.
Second, microresonator-based modulators will require additional thermal tuning. This part will consume around
50 fJ/bit for each microresonator in a state-of-the-art monolithic electronic-photonic platform.

16. Conclusion
A kind of photonics-assisted computing architecture is proposed
with an experimental demonstration at 20 GHz. Computing at a
higher speed while with lower power consumption has proved to
be possible with the help of light. Advanced fabrication techniques
could assist to further integrate electronics and photonics onto a
single chip. In addition, equivalent Moore’s law in integrated
optical computing is expected to scale the circuit with several
directions provided. Emerging optical–electrical–optical devices
have the potential to be integrated with the proposed architecture
to realize more complex computing functions. Further integration
of optical computing units, optical inter/intra-chip optical
interconnect, and optical clock distribution can be explored to
realize an entire all-optical computing system.