DFR Conference, March 2019

9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com
Warranty-Reliability-Durability
How Optimal+/Sherlock Allow for
Comprehensive Prediction Throughout
the Product Lifecycle
March 25th 2019
Dan Sebban (Optimal+) & Ashok Alagappan
(DfR)

DfR Solutions and Optimal+ value proposition
• Industry Trends
− More safety-critical applications require tighter reliability specifications
− Higher level of innovation drives complexity in design and manufacturing
• Industry Challenge
− A primary issue is complexity of modeling intrinsic failures that are induced
by latent defects
− Integrated circuit (IC) field failure rates show gap between design models
and actual performance
• Understanding and closing gap will improve product performance and
reliability prediction methods
2

DfR Solutions and Optimal+ value proposition
(cont.)
• DfR Solutions and Optimal+ will bridge this
gap
DfR Solutions Design-based IC Wearout/Aging
+
Optimal’s Manufacturing-based Reliability
Index (RI)
• Design and Manufacturing feedback will be
combined
− New RI will be a combination of Design
(systematic failures) and Manufacturing (random
failures) 3

Outline
• Optimal+ Reliability Index Methodology
− Introduction of Methodology
− Actual Use Case
− RI feedback to Design model
• Improvement of DfR Modeling using Optimal+ feedback
− 4 stages approach
• Optimal+ and DFR Joint Proposition
4

APQP Process – IATF 16949 Requirement
Semiconductor product design and manufacturing are required to follow APQP and ISO 26262
specifications for Safety-critical applications (e.g. Automotive)
Mass Production
Feedback assessment and Corrective action
Phase 1:
Product
Definition:
Phase 2:
Product
Design
Phase 3:
Process
Design
Phase 4:
Product and
Process
Verification
and
Validation
Phase 5:
Feedback,
Assessment
and
Improvement
Feedback loop is usually reactive and complex to implement

Specs
Char.
Reliability
Performance
Field Failure
data
Design  Reliability Model
Manufacturing 
Reliability Performance
Current situation
• Design and Manufacturing are ‘Siloed’
• Reliability specifications are ‘one-time’ delivered at qualification to mfg.
• Reliability is monitored on reactive base
• Gap between Actual and Modeled reliability performance
Phase 4:
Product and
Process
Verification
and
Validation
Phase 5:
Feedback,
Assessment
and
Improvement
Mass Production
O+ O+
A Reliability digital-thread between design and manufacturing is imperative
Phase 1:
Product
Definition:
Phase 2:
Product
Design
Phase 3:
Process
Design
DFR DFR

Actual Failure Rate vs. Model
When tracking the actual failures (either field or manufacturing), we usually can see a gap
between the model and the actual performance.
7

Manufacturing Reliability-Index
• IC manufacturing has limited capability of differentiation
between good parts of differing quality (e.g. usage of
different good Soft Bins)
• Current methodologies are discrete and take into account
relatively small part of manufacturing data (i.e. test
information)
− Cannot distinguish between ‘levels’ of good parts
• Optimal+ has analytical methodology that derives a
manufacturing Reliability Index (RI)
− Rank of “goodness” for each IC based on its manufacturing history
− Index is computed using supervised machine learning algorithm
based on downstream response such as customer return, system
level test or burn-in testing
8
Test
Defectivity
and
Metrology
Machine /
Sensor
The input to the manufacturing
Reliability Index

Use Case:
Manufacturing RI for
adaptive burn-in
9

Use Case - Manufacturing RI for adaptive burn-in
• Burn-In is done as part of Manufacturing flow to meet automotive requirements
• The customer request is to reduce the cost of Burn-In without impacting Product Reliability
• Using Reliability Index, we can define which parts are not likely to fail and could skip Burn-In
Production Test Burn-In Ship to
customer
Pass Pass
Current
Flow

Production Test Burn-In Ship to
customer
Pass PassML
Model for RI
Response dataInput data
Proposed
Flow
Use Case - Manufacturing RI for adaptive burn-in
• Burn-In is done as part of Manufacturing flow to meet automotive requirements
• The customer request is to reduce the cost of Burn-In without impacting Product Reliability
• Using Reliability Index, we can define which parts are not likely to fail and could skip Burn-In
Skip

Use Case - Reliability Index ML Modeling
Process
12
E-Test
200 features
Wafer Sort
3,000 features Feature
reduction
(Big data
Analytics)
Supervised
Multivariate
feature
selection
ML
Modeling
Model
Validation
O+ Domain
Knowledge
Final Test
4,000 features
Manufacturing
100 features
3,000
features
~7,500
features
O+ selection of
Supervised
Algorithms
Cumulative Map of Burn-in failures
Model
O+ Domain
Knowledge
100
features
Training data:
48,000 units
25 units failed in burn-in
(80% of Mechanism A)
Validation data:
1,000,000 units
6 units failed in burn-in
(20% of Mechanism A)

Adaptive Burn-In Use Case - Results
• ML model provides RI for each IC
• ML model shows opportunity of
skipping Burn-In by 20% with 0
impact on DPPM
13
BI Skip Rate % 5% 10% 15% 20% 25% 30% 35% 40% 45% 50%
ML Model selection
(DPPM)
0 0 0 0 0.1 0.6 0.6 0.7 1.0 1.2
Random selection
(DPPM)
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
RI threshold
Reliability-Index

Revealing ‘most important features’
• In addition to the actual score (RI) for each IC, ML model reveals ‘most important features’ impacting the
result prediction
• In this use case, the top 30 features cover ~ 95% of the predictive power of the ML model
14
Top 30 features explaining the RI

Expanding the Reliability-Index Concept to Design for
Reliability
We can now feedback RI ML model ‘most important features’ to:
− Manufacturing  this allows to understand whether some retarget or further screen is needed on the current
product
− Design  this allows to take that information into account in the Design for Reliability model of the next generation
product
15
Production
& Test
Burn-In Ship to
customer
Pass PassML
Model for RI
Response dataInput data
Design
‘most
important
features’
Skip

DfR IC Prediction using
Optimal+ Reliability Index
16

Industry Challenge
• High Temperature Operating Life (HTOL) is not effective for intrinsic (non-defect related) reliability
− TDDB: Analog circuits are challenging to accelerate
− EM: Cannot be accelerated with voltage (current density may not directly correlate with I/O or Core voltage)
− HCI/BTI: Robust coverage requires impractical number of separate, mutually exclusive stress legs
• Additional coverage and confidence must come from design validation
− Default design validation tends towards the nominal
− Aging and the impact of aging is state dependent
• Design validation requires N1 Stress Conditions x N2 Measurement Conditions
− In today’s SoC designs, as the complexity of the process explodes, validation increasingly dependent on
designer’s judgement
17
W/C Measurment Conditions
SSG, VMIN, -40C SSG, VMIN, -40C SFG, VMIN, -40C FSG, VMIN, -40C SSG, VMIN, -40C SSG, VMIN, -40C SFG, VMIN, -40C FSG, VMIN, -40C
Drive A->Y Rise Drive A->Y Fall DC Distortion DC Distortion Receive Y->Q Rise Receive Y->Q Fall Y->Q DC Distortion Y->Q DC Distortion
Stress Conditions
VMAX, 125C Drive FMAX clock waveform
VMAX, 125C Drive Static 0
VMAX, 125C Drive Static 1
VMAX, 125C Tri-State
VMAX, 125C Receive FMAX clock waveform
VMAX, 125C Receive Static 0
VMAX, 125C Receive Static 1

Stage 0
• Current methodology of DfR Solutions’ IC wearout prediction
− Failure rate is not constant (gradual increase over time)
− All failure mechanisms (EM, TDDB, BTI, HCI) are relevant to failure rate
− Working around IP limitations (design parameters, manufacturing data) requires an
acceleration transform approach
− Focus is providing a maximum failure rate demonstrated through HTOL testing
• Provides value to end user who has limited information about the IC
component
− Method is an improvement over current ‘marketing-type’ guidance for users of IC
components (constant failure rate assumption, single activation energy, etc.)
− Requires process node, technology (planar or FinFET), test conditions, test results, and
operating conditions
• Inputs and outputs of the module are shown in the next slide
18

Stage 0 (Inputs and Outputs)
19
Required Inputs
Output – Life prediction plot
Analysis Options
Life prediction as
a function of four
Intrinsic semiconductor
Failure mechanisms

Stage 1: Part-Specific Parameters
• DfR and Optimal+ will enhance modeling capability based on actual
design/process parameters. Initial list of parameters will initially include
− Transistor types in the core and periphery, gate length and width
− Type of gate dielectrics and equivalent oxide thickness
− Type of metallization, width and thickness
− Type of substrate
− Applied voltage in core and periphery, applied frequency and duty cycle
• Prediction models will be optimized based on these parameters
• Integration allows failure rate prediction to be more part-specific
− Recognizes those suppliers focused on the aerospace, automotive, defense, and other
high-performance (AADHP) industries
20

Stage 1: Part-Specific Parameters (cont.)
Stage 0 (Current Approach)
• Device parameters (gate dielectric, oxide
thickness, metallization) are obtained from
ITRS roadmap
− Assumes transistor types and
parameters are constant throughout the
die
• Assumes constant bias (voltage) conditions
throughout the die
• Model parameters are obtained from
JEDEC/literature
21
Stage 1
• Device parameters (gate dielectric, oxide
thickness, metallization) are obtained from actual
product design and process
− Effective gate lengths (Leff - typically short
channel) and equivalent gate oxide thickness
(EOT - typically thin oxide) in the core of the
circuit
− Effective gate lengths (Leff - typically long
channel) and equivalent gate oxide (EOT –
typically thick oxide) in the I/O of the circuit
• Operating bias conditions are obtained from the
product core and periphery circuit blocks
• Model parameters are obtained from
product test data or JEDEC/literature

Stage 1: Part-Specific Parameters (cont.)
• Enables partitioning of component and models by Input/Output (Periphery)
and Core
• Models, model parameters and applied bias conditions will change based on the
transistor type in the circuit
• For example,
𝐴𝐹𝐼𝑂 =
DCtest
DCuse
n
eɣ(1/Vuse – 1/Vtest) e-Ea/K(1/Tuse-1/Ttest)
𝐴𝐹 𝐶𝑜𝑟𝑒 =eɣ(1/Vuse – 1/Vtest)*eEa/K(1/Tuse-1/Ttest)
− Note change in models and exponents (negative and positive Ea)
− Instead of core and periphery, this approach could also evolve into specific functional
blocks
• Locked IP approach (already implemented in Sherlock) allows for use of
these parameters without revealing proprietary information
22
DC – Duty Cycle, Vuse and Vtest are applied and test bias
conditions, Ea is activation energy, ɣ is voltage exponent, Tuse
and Ttest are applied and test temperature

Stage 2: Failure Mode Specific Prediction
• Extension of the method demonstrated in stage 1, but with modified approach to
model aging and wearout mechanisms separately
− Aging is a gradual parameter shift in the device with a well behaved time dependency. Examples
include Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI)
− Wearout is a stress induced phenomenon resulting in random or sudden failure. It is very
dependent on defect rate of a population. Examples include Time Dependent Dielectric
Breakdown (TDDB) and Electromigration (EM)
• Device properties obtained from Optimal+ will be used to determine parameter
degradation for aging mechanisms and failure rate for wearout mechanisms
• Stage 2 will enable Tier 1 and OEMs to implement system-level mitigations based
on the failure mode
− Reduction in environmental stress, adjustment in signal incorporation, prognostics, etc.
23

Stage 2: Failure Mode Specific Prediction (cont.)
• Modeling of transistor types in the critical path of the circuit, as determined by
design/process
• Aging: Instead of failure rate calculation, transistors will be modeled to
predict degradation of performance metrics (e.g., threshold voltage / Vt,
drive current / Idsat, and transconductance / gm)
− Device parameters (Leff, gate oxide thickness, Vd) obtained from Stage 1 will be used
− Models will determine the percentage shift from baseline value (such as 10% increase)
obtained from design/process with respect to field usage conditions resulting in a
Pass/Fail criteria
− For example, Idsat = Leff
 exp(-/Vd) exp(-Ea/KT) tn
• Wearout: Failure rate will be calculated based on the above approach
24
Idsat is change in saturation current, Leff is effective length, T is
temperature, t is stress time,  is voltage acceleration factor, Vd is
drain voltage

Stage 3: Population-Based Prediction
• Manufacturing and test data will be leveraged to determine the rate of
parameter shift across a large fielded component population
− ‘Most important features’ determined from manufacturing RI can be used
− Data mining parameters and metrics corresponding to failure mechanisms
• Will allow for continuous feedback loop between manufacturing and design
• This approach has the potential to provide the highest level of accuracy
− Failure rate prediction now becomes based on individual, instead of average, device
characteristics
25

Stage 3: Population-Based Prediction (cont.)
• Leverages final parametric test data as determined from
Manufacturing RI
− For Aging, different transistor types and gate oxide thicknesses will
be considered
› Final parametric test data includes but not limited to threshold voltage,
drive current, and substrate current (Isub)
− For wearout, structural/material properties from metrology and
parametric test data will be used, including gate oxide
capacitance, gate leakage, and metal resistance (M0 to Mn)
• For Example,
− TFdc = A0 (Isub/W)-n
• Distribution of manufacturing data will be used to model the percentage shift
outside the tolerance of the product for given field conditions
26
Shifted
distribution as
predicted by the
model for
field conditions
Baseline
distribution
TF is Time to Failure, Isub is substate current, W is transistor
width – Obtained from parametric test data and
metrology/design

Specs
Char.
Reliability
Performance
Field Failure
data
Enhanced Design for Reliability
Model
Manufacturing 
Reliability Performance
Optimal+ and DFR Joint Proposition
• Establish a Reliability digital-thread across product lifecycle
• Feed reliability performance backward and forward in real-time all the time!
• Enhance DFR modeling with reliability ‘most important features’ from Manufacturing
Phase 4:
Product and
Process
Verification
and
Validation
Phase 5:
Feedback,
Assessment
and
Improvement
Mass Production
O+ O+
Phase 1:
Product
Definition:
Phase 2:
Product
Design
Phase 3:
Process
Design
DFR DFR
Reliability ‘most
important features’

Speaker Slide
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