Uploaded bySeyed Amir Alavi
Firmware Co-Design & Development for IP Cores in C++/SystemC using Verilator
The document outlines a conference presentation by Dr. Seyed Amir Alavi on firmware co-design and development for IP cores using C++ and SystemC, focusing on the utilization of Verilator for simulation. It discusses key concepts of co-design, motivations for a concurrent hardware/software development process, and introduces SystemC as a modeling language for embedded system design. Additionally, the presentation covers advanced use cases and provides a tutorial on employing various tools like Verilator and GTKWAVE in the design process.
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Firmware Co-Design & Development for IP Cores in C++/SystemC using Verilator
- 1. w w w. e m b e d d e d o n l i n e c o n f e r e n c e . c o m Firmware Co-Design & Development for IP Cores Dr Seyed Amir Alavi in C++/SystemC using Verilator
- 2. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com AGENDA 1 Co-design of firmware and FPGA IP cores 2 Introduction to SystemC and simulation of logic blocks in C++ 3 How to use Verilator for simulation of IP cores written in Verilog HDL 4 Advanced use- cases: Protecting verilated models and real-time simulation 5 Tutorial: Showcasing usage of Verilator, SystemC, CMake build system, and GTKWave
- 3. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com THE SPEAKER Embedded Software Engineer Focus: Design of embedded software for control systems of quantum computers As an embedded systems engineer, I have designed different types of products in several areas such as the Internet of Things (IoT), industrial control systems, and communication networks. I try to employ the latest technologies for software and hardware development, from embedded Linux to different real-time operating systems, and agile software development processes. Model-based embedded system design and implementation is my main expertise, which I have done during the last several years. I have published several papers in high impact engineering journals and presented my research in top rank conferences around the world. Currently, I am working at Riverlane on the design of control systems for quantum computers. Dr Seyed Amir Alavi https://samiralavi.github.io
- 4. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com The Operating System for Error Corrected Quantum Computers https://www.riverlane.com/vacancies/
- 5. Co-design & developmentof firmware and FPGA IP cores What is co-design? Co-designBest Practices. 1
- 6. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Co-Design Process A common approach for building the prototype (with SW & HW) Requirements Analysis Product Definition HW/SW Functional Decomposition HW Design SW Design Development Fabrication Integration and Testing
- 7. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Co-Design Key Concepts Classic design: • HW/SW trade-offs are limited • Less communicationneeded between HW/SW teams • System integration is time consuming • Costly modificationsduring development Co-Design: • Concurrent development of HW/SW • Integration happens more frequently with simulators • Modification are cheaper • Simulation requires skillset The meeting of system-level objectives by exploiting the trade-offs between hardware and software in a system through their concurrent design. Classic Design Co- Design SW HW SW HW
- 8. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Motivations for Co-Design • Meeting short time to market • Verification starts earlier Catching issues earlier Higher quality • Benefits the design of embedded systems and SoCs, which need HW/SW tailored for a particular application: • Faster integration: reduced design time and cost • Better integration:lower cost and better performance • Verified integration:fewer errors and number of iterations
- 9. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Co-Design Approach for IP Cores
- 10. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Agile Co-Design Process with IP Simulation Requirements Analysis Product Definition HW/SW Functional Decomposition HW Design SW Design Development Fabrication Integration and Testing Simulation (verilator) Simulation (SystemC) Verification Production Release
- 11. Introduction to SystemCand simulation of logic blocks in C++ 2
- 12. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com What is SystemC? • SystemC is a modelling language built as a C++ library • Models software and hardware components • System-level modeling • Abstract analog/mixed-signalmodeling • Architectural exploration • Used for: • Performance modeling • Functional verification • High-level simulation (cycle-accurate) • Open source (Apache License) • Developed by the Accellera Systems Initiative • IEEE Std. 1666-2011 • https://github.com/accellera-official/systemc
- 13. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Component Definitions in SystemC Main classes (features, components) of SystemC • Module • Port • Process • Channel • Event Reference: https://learnsystemc.com/
- 14. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Modules and Channels A SystemC module is: • The smallest container of functionality with state, behavior, and structure for hierarchical connectivity. • A C++ class, which inherits a SystemC basic class: sc_module. • The principle structural building block of SystemC. • Represents a componentof a real system.
- 15. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com SystemC Framework Architecture • Requires a C++ development environment • SystemC basic components: • Core Language • Data Types • Elementary Channels • Transaction Level Modelling (TLM) • Abstracts bus transactions such as AXI bus • The most commonly used level of abstraction • SystemC Verification (SCV) • Used for verification of FPGA IPs • Aims to replace HDL test benches
- 16. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Virtual Platform Modelling (cont.)
- 17. How to useVerilator for simulation of IP cores written in Verilog HDL 3
- 18. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Verilator Verilator is a tool that compiles Verilog and SystemVerilog sources to highly optimized cycle-accurate C++ or SystemC code. • Time evolution is cycle-based • No circuit timing (analog propagation time is 0) • Extremely fast simulation • Simulates what SW expects from the HW • Only synthesizable Verilog/SystemVerilog code (few exceptions) • Verilator is open-source and free both as in free beer and free speech https://verilator.org/
- 19. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com SystemC Hello World
- 20. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com SystemC Module
- 21. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Top Package with Test Bench
- 22. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Compilation, Linking, and Simulation
- 23. Advanced use cases •Sharing Protected IPs with Verilator • Co-Simulation of System with QEMU 4
- 24. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Sharing Protected IPs with Verilator Vendordependent approach Example:Xilinx Verilatorapproach
- 25. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com Co-Simulation of System with QEMU Example reference with Xilinx tools Source: Xilinx Quick Emulator:User Guide (UG1169)
- 26. Tutorial Showcasing usage ofVerilator, SystemC, CMake build system, and GTKWave Source code available here: https://github.com/samiralavi/fw-codesign-eoc-2022 5
- 27. © E mb e d d e d O n l i n e C o n f e r e n c e . c o m A l l r i g h t s r e s e r v e d EmbeddedOnlineConference.com References I have used the following references in making the slides: • System On Chip Design Introduction, Hao Zheng, 2010 • Hardware-Software Codesign,Pao-Ann Hsiung, 2005 • DPI Protected Verilog Instead of Encryption, Todd Strader, ORConf 2019 • https://veripool.org/verilator/documentation/ • https://www.xilinx.com/ • https://accellera.org/ • https://learnsystemc.com/ • https://www.itsembedded.com/dhd/
- 28. w w w. e m b e d d e d o n l i n e c o n f e r e n c e . c o m
- 29. w w w. e m b e d d e d o n l i n e c o n f e r e n c e . c o m THANK YOU