Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.

Clock Generator/Jitter Cleaner with Integrated VCOs


Published on

This training module provide a basic understanding of how clocks work and the various functions & key parameters of clocks, and introduces the CDCE62005 clock generator

Published in: Technology, Business
  • Be the first to comment

Clock Generator/Jitter Cleaner with Integrated VCOs

  1. 1. Clock Generator/Jitter Cleaner with Integrated VCOs <ul><li>Source: T EXAS I NSTRUMENTS </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module provide a basic understanding of how clocks work and the various functions & key parameters of clocks, and introduces the CDCE62005 clock generator. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Introduction to Clocks </li></ul></ul><ul><ul><li>Clock Functions </li></ul></ul><ul><ul><li>Clock Parameters </li></ul></ul><ul><ul><li>CDCE62005 introduction </li></ul></ul><ul><ul><li>CDCE62005 implementation </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>19 pages </li></ul></ul>
  3. 3. Clocks in the Signal Chain Power Management Signal Conditioning Temperature Pressure Position Speed Flow Humidity Sound Light The Real World Analog Signal Conversion to Digital Digital Signal Conversion to Analog Signal Conditioning Interface Clocks DSP/FPGA/ASIC
  4. 4. Introduction to Clocks <ul><li>What is a Clock? </li></ul><ul><ul><li>A device that generates periodic signals for timing. </li></ul></ul><ul><li>What types of systems require a clock? </li></ul><ul><ul><li>Any system that requires a reference to time for synchronization, command execution, and data transfer. </li></ul></ul><ul><li>How does the clock fit into the signal chain? </li></ul><ul><ul><li>Clocks are connected to anything that processes a signal in the digital domain. Therefore, clocks are needed to connect the DSP/FPGA/ASIC, Data Converters, and Interface components . </li></ul></ul><ul><li>What role does the clock play in the system? </li></ul><ul><ul><li>The clocking network provides the frequency inputs to the various devices within a system allowing them to perform their intended function. </li></ul></ul>
  5. 5. How Does a Basic Clock Work? <ul><li>A clock receives an input frequency from a source and either distributes that frequency or generates new frequencies to send as outputs to other devices within the system. </li></ul><ul><li>Non-PLL clocks are used when the time delay between source and output, known as a propagation delay, is not important to the system. </li></ul><ul><li>PLL Clocks are used when the system needs to minimize the propagation delay. PLL’s allow a clock to: </li></ul><ul><ul><ul><li>Eliminate propagation delay </li></ul></ul></ul><ul><ul><ul><li>Allows Phase Adjustments </li></ul></ul></ul><ul><ul><ul><li>Perform Integer or Fractional Multiplication </li></ul></ul></ul><ul><ul><ul><li>Make Duty Cycle Corrections </li></ul></ul></ul><ul><ul><ul><li>Remove noise from the reference clock with jitter cleaning. </li></ul></ul></ul>Phase/Freq Detector (PFD) Loop Filter VCO  P1  P2  Pm  M Input Clk1 Clk2 Clkm  N PLL Design
  6. 6. Clock Functions <ul><li>Fanout Buffers – clock distribution </li></ul><ul><li>Multipliers/Dividers – clock distribution & generation </li></ul><ul><li>Synthesizers – clock distribution & generation </li></ul><ul><li>Jitter Cleaners </li></ul>Clock Distribution Clock Generation Clock PLL Feed- back PLL /N /M /P PLL1 /P1 /P2 /P3 /P4 PLL2 Osc
  7. 7. Jitter Cleaner Jitter Cleaner: Any PLL-based clock that cleans the noises from the reference clock and provides a clean and synchronized signal for the receivers using an external VCO (VCXO) or internal VCO. Ideal Input clock: Real Input clock with Jitter: Jitter Cleaning using a VCXO VCXO Ideal Input clock: Clean Clock: LPF CDC V304
  8. 8. Clock Parameters <ul><li>What are the key characteristics of a clock? </li></ul><ul><ul><li>Signaling Level (Pre-Defined by the Receivers in the System) </li></ul></ul><ul><ul><ul><li>Single-Ended: LVCMOS,TTL, LVTTL – Up to ~250 MHz </li></ul></ul></ul><ul><ul><ul><li>Differential: LVDS, LVPECL, CML, PCI Express (HCSL), SSTL, HSTL - Up to 10+ GHz </li></ul></ul></ul><ul><ul><li>Performance </li></ul></ul><ul><ul><ul><li>Jitter: Common Range of <200 fs – 100 ps </li></ul></ul></ul><ul><ul><ul><li>Propagation Delay: Common Value of ~3 ns </li></ul></ul></ul><ul><ul><ul><li>Output Skew: Common Range of 100 – 500 ps </li></ul></ul></ul><ul><ul><li># of Outputs: Common Range of 1-24 Channels </li></ul></ul><ul><ul><li># of Frequencies: Can be equal to # of channels </li></ul></ul><ul><ul><li>Input Voltage: Common Range of 1.2 – 5 V </li></ul></ul><ul><ul><li>Input Frequency </li></ul></ul><ul><ul><li>Output Frequencies </li></ul></ul>
  9. 9. Jitter <ul><li>Period Jitter </li></ul><ul><ul><li>The deviation in cycle time of a signal with respect to ideal period over a random sample of cycles. This is also referred to as short-term jitter. </li></ul></ul><ul><li>Cycle-to-Cycle Jitter </li></ul><ul><ul><li>the variation in cycle time of a signal between consecutive cycles, over a random sample of successive cycle pairs. Also known as adjacent cycle jitter. </li></ul></ul><ul><li>Phase Jitter </li></ul><ul><ul><li>The integrated value from phase noise plot in time over a specific band of frequencies. This is long term jitter. </li></ul></ul>Cycle-to-Cycle Period Jitter
  10. 10. Propagation Delay Propagation delay time, t pd : The time between the specified reference points on the input and output voltage waveforms with the output changing from one defined level (High or Low) to the other defined level. It is common to have a propagation delay of ~3 ns. t pd = t PHL or t PLH
  11. 11. Output Skew Output Skew, t sk(o) : The difference between any two propagation delay times when input switching causes multiple outputs switching. Common output skew can range anywhere from 100 ps to 500 ps.
  12. 12. CDCE62005 Clock Generator / Jitter Cleaner <ul><li>Integrated frequency synthesizer including PLL, multiple VCOs and loop filter </li></ul><ul><li>Fully Configurable Outputs Including Frequency, Output Format, and Output Skew </li></ul><ul><li>Smart Input Multiplexer Automatically Switches between One of Three Reference Inputs </li></ul><ul><li>Excellent Jitter Performance </li></ul><ul><li>Integrated EEPROM Determines Device Configuration at Power-up </li></ul><ul><li>Multiple Operational Modes Include Clock Generation via Crystal, SERDES Startup Mode, Jitter Cleaning, and Oscillator Holdover Mode. </li></ul>
  13. 13. Common Applications <ul><li>Communications </li></ul><ul><ul><li>Very Low Jitter </li></ul></ul><ul><ul><li>High Performance Requirements </li></ul></ul><ul><ul><li>Generally differential inputs to support higher speeds </li></ul></ul><ul><li>Consumer </li></ul><ul><ul><li>Frequency Accuracy (0 PPM translation Error) </li></ul></ul><ul><ul><li>Low Power </li></ul></ul><ul><ul><li>Different/Multiple Clock Frequencies </li></ul></ul><ul><ul><li>Medium Jitter Performance </li></ul></ul><ul><ul><li>Frequency Synchronization </li></ul></ul><ul><ul><li>Low Cost </li></ul></ul><ul><ul><li>Market on Time </li></ul></ul><ul><li>Medical Electronics </li></ul><ul><li>Military and Aerospace </li></ul><ul><li>Industrial </li></ul>Servers Video Surveillance HDTV Wireless Basestations
  14. 14. Block Diagram
  15. 15. CDCE62005 Application Example
  16. 16. CDCE62005 Interface to ADC Figure 1 Figure 2
  17. 17. LAN Clock Generation
  18. 18. WAN Clock Generation
  19. 19. Additional Resource <ul><li>For ordering the CDCE62005, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li> </li></ul></ul>Newark Farnell