1. Analysis of Diode Emulation in Light Load Condition
of Synchronous Buck Converter
Yang Chen, Peyman Asadi and Parviz Parto, International Rectifier, U.S.A.
Abstract
Light load efficiency becomes an important factor to evaluate synchronous Buck converters. Constant
on-time control reduces switching frequency at light load, switching losses decreases and system effi-
ciency increases. However, the variable switching frequency used in constant on-time control limits its
application in some areas, where constant switching frequency is required. This paper investigates
Diode Emulation (DE) operation in light load condition, especially from output voltage ripple, inductor
current ripple, transient response, and power loss points of view. Analysis shows smaller output volt-
age ripple and inductor current ripple, and less power losses in DE operation. However extra transi-
tions for switching-in or -out of DE operation cause additional overshoot and undershoot on output
voltage. A feasible scheme is proposed to separate DE transition from the regular load transient for
reducing overshoot. Experiments have been conducted to verify the effectiveness of the analysis and
the proposed scheme in this paper.
1. INTRODUCTION
High efficiency over entire load range, low output
ripple, fast response to the load transients, small
size, and low cost are common design require-
ments for Point of Load (POL) applications.
These design objectives are usually conflicting
and providing an optimum solution is a chal-
lenge. Among these targets, design with highest
possible efficiency has gained more importance
recently. Minimizing power losses at heavy load
currents would result to lower heat dissipation,
smaller solution, and better efficiency. However,
with the advances in power management tech-
niques, POLs are usually operating at light load,
most of the time. Thus, achieving high efficiency
both at light load and heavy load currents is es-
sential for conserving energy and being compli-
ance with “energy-star” regulations [1].
Synchronous Buck converter is the most com-
monly used topology for delivering power in POL
applications (Fig. 1). At heavy load where it is
operating in Continuous Conduction Mode
(CCM), the conduction loss is the dominant loss
and it can be reduced by using a Synchronous
Field-Effect Transistor (FET) with low Rdson (turn-
on resistance of FETs). Unfortunately, these
FETs have higher gate charges. This results to
lower efficiency at light load, where the switching
losses are dominating.
Several methods [2- 6] have been reported to
reduce power loss at light load. Pulse-skipping
and variable switching frequency methods are
common techniques to reduce the switching fre-
quency at light load [3, 4]. These methods miti-
gate the switching losses in FETs and their driv-
ers at light load. However, lower the switching
frequency results to increase in the output volt-
age ripple and slower dynamic response during
load transients.
In [5], a combination of different MOSFETs and
drivers in parallel are used for light, medium, and
heavy load current ranges. Each MOSFET and
its driver are optimized for a particular operating
section. Although this method improves the effi-
ciency effectively, using redundant hardware
makes it impractical for many POL applications.
An effective method for increasing light load effi-
ciency is Diode Emulation (DE). In this method,
the Synchronous (Sync) FET is turned off when
inductor current hits zero. One advantage of this
method is that the converter is always operating
with fixed switching frequency. This method is
simple and doesn’t require extra hardware. In
this paper, the detailed analysis of the operation
of synchronous Buck converter with Diode Emu-
lation, the inductor ripple current and output volt-
age ripple, the power stage losses is presented.
A feasible scheme is proposed to improve the
transient response while the converter goes into
in Discontinuous Conduction Mode (DCM) mode
in a load step-down transient. And finally, ex-
periments are presented to verify the effective-
ness of the analysis and the proposed scheme.

2. 2. OPERATION OF DIODE
EMULATION
In a synchronous Buck converter as in Fig. 1,
when the inductor current IL drops to zero at light
load condition, the synchronous (Sync) FET is
turned off. By this means, IL doesn’t flow in re-
verse direction as shown in Fig.2. In order to de-
tect the reserve inductor current, voltage drop
across drain and source of Sync FET, i.e. the
switch node (SW) voltage, is monitored. This
method is also called Rds(on) current sensing.
When Sync FET is on and Vsw>0, a reverse cur-
rent condition is recognized. And then Sync FET
is turned off. The advantage of this type of cur-
rent sensing method is: there is no any external
current sensing device or shunt resistor. So this
method is cost-effective and lossless.
Vo
IL
Vin
UG
LG
Ctrl
FET
Co
Io
Sync
FET
SW
Fig. 1. Synchronous Buck Converter
Fig. 2. Operation Waveforms in DE
2.1. ANALYSIS OF DIODE EMULA-
TION
A. VOLTAGE AND CURRENT RIPPLE ANALY-
SIS
Figure 3 shows typical inductor current and out-
put voltage ripples in light load condition. Fig.
3(a) is Diode Emulation operation, or DCM op-
eration, while Fig. 3(b) is Diode Emulation dis-
abled, or CCM operation. The dashed line repre-
sents the average inductor current <IL>. It equals
the dc load current Io. In Fig. 3(a) the peak cur-
rent Ipk(DCM) and ripple voltage ∆Vo(DCM) can be
calculated as in (1). Here the voltage ripples
caused by ESR and ESL of Co are neglected
since ceramic capacitors are usually used in
POL circuits. Similarly, the ripples in Fig.3(b)
can be obtained as in (2). Comparing (1) and (2),
it can be found that ripples in DCM are related to
the load current. Thus, in very light load condi-
tion, when Io is small, DCM could have smaller
ripples than those of CCM. With the increase of
Io, ripples in DCM increase accordingly and
eventually will be equal to the ripples of CCM,
when Buck converter comes into the critical con-
dition between DCM and CCM.
a. DCM
IL
Vo
<IL>= Io
0
0
A’
B’
2∆Vo(CCM)
2∆i(CCM)
DTs
Ts
b. CCM
Fig. 3. Voltage and Current Ripples of DCM vs.
CCM
LV
TIVVV
I
VVCV
IILV
V
in
sooino
DCMpk
oino
oDCMpkin
DCMo
)(2
)(2
)(
2
)(
2
)(
)(
−
=
−
−
=Δ
(1)

3. B. TRANSIENT REPONSE
In traditional Buck converter with CCM operation,
the power stage circuit behaves as a second-
order system with double poles generated by L
and Co. A type III compensator is usually se-
lected to stabilize the overall control loop. In DE
operation, the inductor current goes to zero in
each switching cycle, so the power stage be-
haves as a first-order system [7]. However, due
to the different duty cycles in DCM and CCM with
the same load current, the voltage level of error
amplifier output, as one of the comparison sig-
nals in PWM generation, becomes different.
Thus, the load step-down transient response be-
comes complicated. If DE is enabled as soon as
the inductor current drops to zero, the converter
faces both a load transient and a CCM-to-DCM
transition, which would cause a larger overshoot.
One of the feasible solutions is to keep CCM op-
eration until load transient ends, which separates
the above two events and thus reduces the
overall overshoot. A feasible scheme based on
the above analysis has been proposed: at load
step-down transient, when the converter first de-
tects a reverse inductor current situation, a 128-
switching-cycle delay is inserted before DE op-
eration really takes place. Experiments in Sec-
tion 3 verify the effectiveness of this scheme.
C. POWER STAGE LOSSES
In Diode Emulation, Sync FET is turned off as
soon as inductor current flows in the reverse di-
rection. Thus, the conduction loss, from LG turn-
off to the end of that switching cycle, is saved.
So is the conduction loss in the inductor. Addi-
tionally, MOSFET switching loss, body diode
conduction loss, output capacitance loss and in-
ductor core loss have corresponding changes.
These losses can be treated as power stage
losses and the detailed comparison of the differ-
ence between DCM vs. CCM is listed in as be-
low (for the range of 0A < Io < ∆i(CCM)). Gate driv-
ing loss remains approximately the same for both
cases, and it is not covered in this paper.
1) MOSFET Conduction Loss: from Section A,
the ripple current in DCM is smaller than that in
CCM under the same condition. This results in a
lower rms current for DCM, which causes less
conduction loss. As mentioned above, the Sync
FET and inductor conduction loss can be further
saved by turning off LG when IL starts flowing in
reverse direction. Conduction loss can be calcu-
lated as following: where Rds(on) is the turn-on re-
sistance of the control (Ctrl) FET and Sync FET.
For DCM:
so
o
in
o
oinin
o
DCMpksyncondsDCMsynccond
DCMpkctrlondsDCMctrlcond
TV
IL
K
VD
VK
D
VVV
KV
D
D
IRP
D
IRP
⋅
⋅
=
⋅
⋅
=
−
=
⋅⋅=
⋅⋅=
2
,
)(
where
3
3
1
2
2
1
2
)(
2
_)()(_
1
)(
2
_)()(_
For CCM:
timedeadbandtheist,/where
)/21(
)
3
1
(
)
3
1
(
dead
2
)(
2
_)()(_
2
)(
2
_)()(_
ino
sdead
CCMosyncondsCCMsynccond
CCMoctrlondsCCMctrlcond
VVD
TtD
iIRP
DiIRP
=
−−⋅
⋅Δ+⋅=
⋅Δ+⋅=
2) MOSFET Switching Loss: for DCM, Ctrl FET
turns off with peak current at point A (A, A’ B, B’
are referred to Fig. 3(a) and Fig. 3(b)), which is
the only point to incur switching loss; for CCM,
Ctrl FET has turn-off loss as in DCM, and Sync
FET also has it because at point B’ the reverse
inductor current is cut off from Sync FET and
flows into the bode diode of Ctrl FET. The Sync
FET turn-off loss decreases with the increase of
the load and finally drops to zero when <IL>=
∆i(CCM). Additionally, DCM has a smaller peak
current, which helps to reduce switching loss fur-
ther. So the switching loss of DCM is smaller.
Their switching losses can be calculated as be-
low:
For DCM:
sctrlfDCMpkinDCMctrlswitch FtIVP ⋅⋅⋅= _)()(_
2
1
For CCM:
ssyncfCCMoinCCMsyncswitch
sctrlfCCMoinCCMctrlswitch
FtiIVP
FtiIVP
⋅⋅Δ−⋅=
⋅⋅Δ+⋅=
_)()(_
_)()(_
||
2
1
)(
2
1
where, tf_ctrl is the fall time of the control FET;
tf_sync is the fall time of the synchronous FET. Fs
(=1/Ts) is the switching frequency
L
DTVV
i
LCV
TVVV
V
soin
CCM
in
sooin
CCMo
)(
2
8
)(
2
)(
2
)(
−
=Δ
−
=Δ
(2)
(3)
(4)
(5)
(6)

4. 3) MOSFET Body diode conduction loss: for
DCM, the Sync FET body diode conduction loss
exists; for CCM, both Ctrl FET and Sync FET
have body diode loss because of the bidirec-
tional flow of the inductor current.
For DCM:
sdeadDCMpksyncSDDCMsyncbd FtIVP ⋅⋅⋅= )(_)(_
For CCM:
sdeadCCMosyncSDCCMsyncbd
sdeadCCMoctrlSDCCMctrlbd
FtiIVP
FtiIVP
⋅⋅Δ+⋅=
⋅⋅Δ−⋅=
)(
||
)(_)(_
)(_)(_
where, VSD_sync is the diode forward voltage of
Sync FET; VSD_ctrl is the diode forward voltage of
Ctrl FET; tdead is the deadband time of Buck con-
verter.
4) MOSFET Reverse Recovery Loss: there is no
reverse recovery loss for both of DCM and CCM
because of the zero-voltage turn-on of the FETs
in this load current range.
5) MOSFET Output Capacitance Loss: when
Buck converter works at a high switching fre-
quency, the losses incurred by charging and dis-
charging the output capacitance (Cds) become
more important. Output capacitance loss exists
when MOSFET is turned on with a certain Vds
voltage across the drain and the source. So in
DCM, Ctrl FET has such a loss at its turn-on
even if it is a zero-current switching. However,
there is no such a loss in CCM because two
switches are turn-on with Vds≈0V. The output ca-
pacitance loss in DCM can be estimated as:
soinctrlossDCMctrls FVVQP ⋅−⋅⋅= )(
2
1
_)(_cos
where, Qoss_ctrl is the output charge of Ctrl FET.
6) Inductor Conduction and Core Losses:
DCM inductor conduction loss can be calculated
as:
inductorofresistancedcisDCR,
2
,
)(
where
3
1
2
2
1
21
)(
2
)(_
so
o
in
o
oinin
o
DCMpkDCMindcond
TV
IL
K
VD
VK
D
VVV
KV
D
DD
IDCRP
⋅
⋅
=
⋅
⋅
=
−
=
+
⋅⋅=
CCM inductor conduction loss can be calculated
as:
ino
CCMoCCMindcond
VVD
iIDCRP
/where
)
3
1
( 2
)(
2
)(_
=
Δ+⋅=
Inductor core loss for both cases can be calcu-
lated as [8]:
(mW))205914.0()(004203.0
(mW))05914.0()(004203.0
28.2
)(
84.1
)(_
28.2
)(
84.1
)(_
CCMDCMindcore
DCMpkDCMindcore
iFsP
IFsP
Δ⋅⋅⋅=
⋅⋅⋅=
From the above quantitative comparison be-
tween DCM and CCM, it can be seen extra
losses exist in CCM operation in the range of
0<Io<∆i(CCM). Theoretical and experiment results
are given in the next section.
3. EXPERIMENTAL VERIFI-
CATION
Figure 4 shows the typical operation waveforms
in DCM and CCM (from top to bottom are: Vo,
inductor current IL, Sync FET gate signal LG).
Both of them are working under conditions of:
Vin=12V, Vo=1V, Io=0.5A, Fs=279kHz, L=0.6uH,
Co=6x22uF. In DCM, LG is switched off after in-
ductor current drops to 0A. Comparing Fig.4(a)
and 4(b), DCM has smaller Vo and IL ripples than
CCM under the same load current.
a. DCM
b. CCM
Fig. 4. DCM vs. CCM operation
(7)
(8)
(9)
(10)
(11)
(12)

5. Figure 5 shows the experiment and calculation
results of the peak-to-peak output voltage and
inductor current ripple respectively. Both theo-
retical and experimental results show that DCM
has smaller ripples than CCM. When Io increases
and approaches to the critical point between
DCM and CCM, their difference becomes
smaller and finally disappears. The test condition
is : Vin=12V, Vo=1V, Io=0.5A, Fs=279kHz,
L=0.6uH, Co=75uF.
Vo ripple (pk-pk) vs. Io
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Io(A)
DeltaVo(V)
DCM(calculationl) DCM(experiment) CCM(calculation) CCM(experiment)
IL ripple(peak-to-peak) vs. Io
0
1
2
3
4
5
6
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Io(A)
IL(pk-pk)(A)
DCM(calculation) DCM(experiment) CCM(calculation) CCM(experiment)
Fig. 5. Vo and IL ripples (peak-to-peak) : calcula-
tion vs. experiment
Figure 6 shows the transient response of load
step up/down. In Fig.6, from top to bottom are: IL,
error amplifier output COMP and Vo. Buck con-
verter can automatically choose CCM or DCM
according to its load. For example, at Io=5A, it
works in CCM, while at Io=0.5A in DCM. For load
step-up on the left side of the picture, Vo shows a
large undershoot because two transients happen
at the same time: load step-up transient and
DCM-to-CCM transition. At load step-down on
the right side of the picture, the converter first
has a load step-down transient in CCM. Then a
128-cycle delay is inserted before it goes into
DCM. And there, the converter experiences a
CCM-to-DCM transition. It can be observed that
the second overshoot is reduced by 50mV com-
pared with the amplitude of the undershoot at
load step-up by using this proposed scheme.
Test condition: Vin=12V, Vo=1V, Fs=600kHz,
L=0.33uH, Co=8x47uF
Fig. 6. Load Step-Up/Down Transient (Io: 5A-
0.5A)
Figure 7 shows the power stage losses from cal-
culation and experiment. Here the power stage
losses only include the MOSFET conduction
loss, switching loss, bode diode loss, output ca-
pacitor loss, and inductor conduction and core
losses. Gate driving losses are not included
here. From experiment, DCM operation has less
power stage loss than CCM in range of 0-0.9A
load in the studied case. The maximum saved
loss is around 130mW. As Io increase above
0.9A, two schemes have almost the same power
loss. Calculation shows relatively lower power
losses than experiment, especially for DCM. The
reason is that a small amount of reverse inductor
current is needed before the converter can de-
tected that it is in DCM. This will incur extra loss
to DCM. Another factor that contributes to the
difference between calculation and experiment is
that the parameters of MOSFET used in calcula-
tion are picked up as typical values. However,
their actual values, in such a light load condition,
usually vary from typical ones. Overall, DE op-
eration shows an advantage over the CCM op-
eration at very light load. Test condition: Vin=12V,
Vo=1V, L=0.3uH, Fs=640kHz.

6. Power Stage Loss vs. Io
0.05
0.07
0.09
0.11
0.13
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0.31
0.33
0.35
0.37
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3
Io(A)
Power(W)
CCM(experiment) DCM(experiment) DCM(calculation) CCM(calculation)
Fig. 7. Power Stage Losses: calculation vs. ex-
periment
4. CONCLUSION
The operation of Buck converter with Diode
Emulation was investigated and its performance
was compared with synchronous operation at
light load. Theoretical and experimental results
are presented and confirm that in light load con-
dition DE method reduces power stage losses
and output voltage ripple and inductor current
ripple meanwhile. This is a great benefit of using
Diode Emulation method with fixed switching fre-
quency for increasing light load efficiency com-
pared to variable frequency methods.
In Diode Emulation mode, the duty cycle is
smaller and the error amplifier output changes.
This would result to additional transition when
toggling between DCM and CCM. Plus the origi-
nal load transient of Buck converter, increased
overshoot and undershoot of the output voltage
during load step-up and down can be observed.
A 128-cycle delay is proposed to reduce over-
shoot during load step-down transient before the
converter goes in to DE mode. Presented results
verify its effectiveness.
5. REFERENCES
[1] Qahouq, J.A.; Huang, L.: Adaptive
Controller with Mode Tracking and
Parametric Estimation, Twenty Second
Annual Applied Power Electronics
Conference and Exposition, APEC’07
Conference Proceedings, pp.1568-1574,
Feb. 25 2007-March 1 2007
[2] Zhou, X.: “Low-voltage High-efficiency Fast-
transient Voltage Regulator Module,” Ph.D.
Dissertation, Virginia Polytechnic Institute
and State University, July 1999
[3] Arbetter, B. ; Maksimovic, D.: “Control
Method for low-voltage DC power supply in
battery-powered systems with power
management“, in Proc. 28th Annu. IEEE
Power Electron. Spec. Conf. (PESC’97),
Jun. 22-27, 1997, vol. 2, pp. 1198-1204, vol.
2, 1997
[4] Zhou, X.; Donati, M.; Amoroso, L.; Lee, F.C.
: “Improved light-load efficiency for
synchronous rectifier voltage regulator
module“, IEEE Transactions Power
Electron., vol. 15, no. 5, pp. 826-834, Sep.
2000
[5] Abdel-Rahman, O.; Abu-Qahouq, J.A.;
Huang, L.; Batarseh, I., “Analysis and
Design of Voltage Regulator With Adaptive
FET Modulation Scheme and Improved
Efficiency“, Power Electronics, IEEE
Transactions on , vol.23, no.2, pp.896-906,
March 2008
[6] Peterchev, A.V.; Sanders, S.R., “Digital loss-
minimizing multimode synchronous Buck
converter control“, Power Electronics
Specialists Conference, 2004. PESC 04.
2004 IEEE 35th Annual , vol.5, no., pp.
3694-3699 Vol.5, 20-25 June 2004
[7] Ma, D.; Ki, W.H.; “Fast-Transient PCCM
Switching Converter With Freewheel
Switching Control”, IEEE TRANS. ON
CIRCUITS AND SYSTEMS—II: EXPRESS
BRIEFS, VOL. 54, NO. 9, SEP. 2007Analog
Devices: Analog Design Seminar. München:
Analog Devices GmbH, 1989.
[8] Vitec Electronics Corporation: Datasheet of
SMD High Frequency Power Inductor
59P9874N
(http://www.viteccorp.com/data/af4263.pdf)