Enhancing Wireless Using SDR

International Journal of Research and Reviews in Computer Science (IJRRCS)
Vol. 3, No. 5, October 2012, ISSN: 2079-2557
1841
© Science Academy Publisher, United Kingdom
www.sciacademypublisher.com/journals/index.php/IJRRCS
Enhancing Wireless Communication using Software-Defined
Radio Architecture
James Agajo1
, Idigo Victor Eze2
, and Nosiri Onyebuchi3
1
Federal Polytechnic Auchi Department of Electrical/ Electronics, Edo State Nigeria
2
Nnamdi Azikiwe University Awka Department of Electronics and Computer Engineering, Anambra State, Nigeria
3
Federal University of Technology Owerri Department of Electrical/ Electronics, Nigeria
Email: agajojul@yahoo.com vicuugo@yahoo.com, buchitelnet12@yahoo.com
Abstract – Software-Defined Radio (SDR) is a rapidly evolving technology that is receiving enormous recognition and
generating widespread interest in the telecommunication industry. It facilitates implementation of the physical and link layer
protocols-in effect entire wireless system,-in software. A side effect of the rapid growth of wireless system technology in the
recent past is an excess of wireless system standards. Therefore the SDR concept is emerging as a pragmatic solution. It aims
to build flexible radio systems which are multiple-Defined Radio architectures as a prototyping, tool for wireless baseband
signal processor implementations is explored. Signal processing implementations is explored. Signal processing architectures
and algorithms for the physical layer of IEEE 802.11g- the latest release from the popular IEEE family of wireless standards-is
developed and simulated in Matlab and Simulink. The integrity of the developed model is verified by measurement of the
constellation versus signal to noise ratio (SNR) and Bit error Rate (BER) versus SNR graph, which are reported. The IEEE
802.11g PHY model is then translated to software (C++) with the aid of Real-Time workshop software tool. The generated
codes can then be targeted on a Digital Signal Processor (DSP) or other programmable hardware modules.
Keywords – SDR, OFDM, DSP, Modulation
1. Introduction
1.1. Background
The astronomical growth of wireless communication in
the last two decades has brought with it new challenges. As
researchers and vendors seek for higher-rate data support in
wireless infrastructure, several innovations for implementing
modulation/demodulation

and encoding/decoding emerge and these ultimately result in
a proliferation of air interface standards (AIS). This poses
great challenges to all stakeholders: equipment
manufacturers, regulators, service providers, users, etc.
Responses to the above challenges and market pressures
are forcing the convergence of wireless standards in one
access device. This convergence would produce a seamless,
ubiquitous wireless network with voice, video, multimedia
and broadband data services traveling across multiple
wireless interfaces providing anytime, anywhere
communications to its users. Such technology would enable
users to always be connected to a network through a single
device which has the ability to run different wireless
standards. This in turn poses no mean challenges at the
different layers of the network, right from the wireless
interface (radio) to the application level. The devices would
have to monitor the different RF signals on different wireless
interfaces and switch to standards appropriately. Also, the
size of the devices would have to be as limited as possible.
Approaching the above challenges by the present way of
implementation where separate hardware resources are
allocated for each of the standards would make the “universal
access devices” bulky and inefficient. Moreover,
upgradeability when new standards emerge would be
impossible. Software-defined radio (SDR) is emerging as a
pragmatic solution to this. SDR is simply a technology where
all the seven layers of a wireless network (from Open System
Interconnection - OSI - model point of view) are
implemented in software.In the traditional radio system, the
upper layers - Application, Presentation, and Session - are
almost always implemented in software; lower layers are a
combination of hardware and software, except the physical
(PHY) layer which is mostly hardware [1]. But in software-
defined radio, layers 7 down to 1 are all implemented in
software.
Programmable processing devices, like: Digital Signal
Processors (DSPs), Field Programmable Gate Arrays
(FPGAs), General Purpose Processors (GPPs),
Programmable system on chip (SOC) or other application-
specific processors [2] [3], are used to run the embedded
software. The use of these technologies allows new wireless
features and capabilities to be added to existing radio systems

J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1842
without requiring new hardware. In addition, multiple
wireless standards can be implemented on the same device.
2. IEEE 802.11 Physical layer
The physical (PHY) layer is the lowest layer (ISO layer 1)
specification of the IEEE 802.11 standard. It is the logical
layer in charge of defining the physical details of the
network, such as electrical power transmitted, modulation
scheme, etc [22]. The original 802.11 standard specifies three
PHY layers. Two of the PHYs facilitate communications in
the 2.4GHz Industrial Scientific and Medical (ISM) band
using Direct Sequence (DS) and Frequency Hopped (FH)
spread spectrum (SS) techniques. The third PHY facilitates
communication over infrared links. As the demand for data
rates continued to increase, several new PHY layer
specifications have been added. These PHY extensions to the
original standard are designated by a letter following the
802.11 name, such as 802.11a, 802.11b, 802.11g or 802.11n.
The letter suffix represents the task group that defines the
extension to the standard [23]. Table 2.1 briefly summarizes
802.11 PHY extensions [12][1][13].
Table 2.1. IEEE 802.11 PHY specifications
IEEE Release Technique Band Modulation Max Rate
(Mbps)
Range
(inside)
(M)
Range
(Outside)
(M)
802.11 1997 FHSS 2.4GHz FSK 2 ≈20 ≈100
DSSS 2.4GHz PSK 2 ≈20 ≈100
Infrared PPM 2
802.11a 1999 OFDM 5.7GHz PSK or QAM 54 ≈35 ≈120
802.11b 1999 DSSS 2.4GHz PSK 11 ≈38 ≈140
802.11g 2003 DSSS, OFDM 2.4GHz PSK,QAM 54 ≈38 ≈140
802.11n Expected
2009
MIMO 2.4, 5.7GHz 248 ≈70 ≈250
Figure 1. Relationship between physical and data link layers.
2.1. Basics of IEEE 802.11g standard
The IEEE 802.11g WLAN standard can be thought of as
an intersection between the 802.11b and 802.11a standards.
Like 802.11b, it operates in the same 2.4GHz portion of the
radio frequency spectrum that allows for license-free
operation on a nearly worldwide basis. 802.11g also
implements DSSS PHY and is also limited to the same three
non-overlapping channels as 802.11b. An important
mandatory requirement of 802.11g is full backward
compatibility with 802.11b, which both provides investment
protection for the installed base of 802.11b clients and
extracts a substantial performance penalty when operating in
this mode [1]. Like 802.11a, 802.11g uses Orthogonal
Frequency Division Multiplexing (OFDM). When coupled
with various modulation types, 802.11g (like 802.11a) is
capable of supporting much higher data rates than 802.11b.
802.11g supports a large set of data rates, in fact all the rates
supported by both 802.11a and 802.11b, as shown in table 2.2
below [5].
Implementation block diagram of IEEE 802.11g baseband
is as presented in figure 2 [10]. Chipsets for implementing
this have been available. Coming chapters will be dedicated
to reducing the hardware implementation to software
implementation using DSP, FPGA or other suitable
reprogrammable platforms.
2.2. Review of Software Defined Radio Architecture.
Software defined radio architectures have continuously
evolved since the inception of flexible radio concept. New
advances in digital components proceed to modify even the
latest designs. An ideal software defined radio (SDR) is
entirely implemented digitally, so that it can be completely
reconfigurable via software. This section explains the generic
SDR architecture that would permit implementation of IEEE
802.11g and other WLAN protocols on a single design.
As shown in fig. 1, a digital radio system consists of three
main functional blocks: RF section, IF section and baseband
section. The RF section consists of essentially analogue
hardware modules while IF and baseband sections contain
digital hardware in a conventional digital hardware radio
system.

Table 2.2. 802.11g data rates, transmission types and modulation schemes. Implementation block
Data Rate (Mbps) Transmission type Modulation scheme
54 OFDM 64QAM
48 OFDM 64QAM
36 OFDM 16QAM
24 OFDM 16QAM
18 OFDM QPSK
12 OFDM QPSK
11 DSSS CCK
9 OFDM BPSK
6 OFDM BPSK
5.5 DSSS QPSK, DQPSK
2 DSSS QPSK
1 DSSS BPSK

Rx
RF Front‐
end
Tx
ADC
DAC
DDC
DUC

Base band
Processing
Antenna
Figure 2. Block diagram of a generic digital transceiver [18][29].
As shown in figure. 2 , a digital radio system consists of
three main functional blocks: RF section, IF section and
baseband section. The RF section consists of essentially
analogue hardware modules while IF and baseband sections
contain digital hardware in a conventional digital hardware
radio system.
2.3. Analogue/Digital Conversion.
ADC and DAC are critical blocks as they are the interface
between the analogue and digital domains. They are largely
responsible for MODEM (modulation/demodulation)
performance and are subject to many constraints. Signal to
noise ratio (SNR) is linked to converter resolution by the
following equation [18]:
SNRAD = 1.76 + 6.02b + 10log (2BW/Fsampling) 2.1
where b is the resolution in bits, Fsampling is the sampling
frequency and BW the bandwidth of interest. The
performance of ADC/DAC is very critical to realization of
any software defined radio. The higher the bandwidth it can
handle, the closer it can be placed to the antenna and the
more ideal the SDR becomes. An ideal SDR has the
ADC/DAC immediately following the antenna, thus
eliminating the RF front-end.
2.4. Digital Down/Up Conversion.
Digital Down/Up Conversion (DDC/DUC) is a
fundamental part of the communication system. Digital radio
have fast A/D,D/A converters delivering vast amount of data,
but in many cases, the signal of interest is a small portion of
that bandwidth.DDC acts as a buffer bridging the speed gap
between the ADC and Digital signal processor on the receive
side while DUC does same on the transmit side. It must be
understood that DDC/DUC may not be necessary in some
systems, depending on the speed gap between the ADC/DAC
and DSP.
2.5. Simulation and Prototyping.
The purpose of simulation and prototyping is to develop
and refine new ideas. The simulation environment offers the
designer a flexible and powerful environment on the
computer. In simulation, communication system parameters
like signal to noise ratio (SNR), modulation types and other
modeling parameters can be clearly specified and easily
changed. The designer has more freedom in exploring the
design space as the simulation environment allows design of
algorithms without the constraints of real-time execution. In
contrast, the prototyping environment connects the design to
the real world. Test data is presented to the system from an
uncontrolled environment using hardware interfaces such as
analog to digital converters which present data of fixed
width. The designer is restricted with limited hardware
resources and the timing and power consumption
requirements. These two are rarely used together in the
design and development process. Instead the design is
developed as a two-step process. As a first step, new
algorithms are developed based on simulation results. The
description of the algorithm is used to develop a prototype in
the second step.
2.6. Simulation and prototyping environments.
Simulation and prototyping of WLAN systems involves
development and integration of several computationally
intensive algorithms to enable different features required by
these systems. The designer is faced with two important
problems. First, simulation of communication systems
involves block diagrams and mathematical equations while
prototyping hardware is programmed in C, C++, assembly or

HDL. Second, simulations often run on a host computer,
while prototypes run on hardware and the powerful features
of simulation cannot be combined with the real-time
constraints of the prototype hardware.
Each algorithm used in the simulation has to be tested
independently before being integrated into a communication
system. Interconnection of different algorithm blocks must be
tested to ensure proper operation with neighboring blocks.
The resulting block diagram must be translated into a
program suitable to execute on the prototype hardware.
Mathematical equations are used in algorithm creation. A
digital signal processor is typically used in prototyping
communication systems which require assembly language or
C programming language to generate an executable routine.
Both simulation and prototyping are inherent in
communication system design, with initial design entry done
on the host and final testing done on the prototyping
hardware.
In a block based system level design, each block is
represented by an equation, which specifies the algorithm
implemented by that block. The proper operation of
individual blocks and the entire system is verified by
simulation. The system is then translated into C or HDL and
compiled to run on DSP or FPGA. The main simulation
environments employed in this thesis are Matlab and
Simulink. The add-on tool, Real Time Workshop, was then
employed for automatic code generation. The prototyping
will involve DSP and other hardware and software tools, but
this is left for future work.
2.7. Use of Constellation Diagram in System Performance
Analysis
Some properties of a modulation scheme can be inferred
from its constellation diagram. The bandwidth occupied by
the modulation signals decreases as the number of signal
points/dimension increases. Hence if a modulation scheme
has a constellation that is densely packed, it is more
bandwidth-efficient than the modulation scheme with a
sparsely packed constellation. The probability of bit error is
proportional to the distance between the closest points in the
constellation. The effects of signal corruption on
constellation diagram are as summarized below.
a) Gaussian noise shows as fuzzy constellation points;
b) Non-coherent single frequency interference shows as
circular constellation points;
c) Phase noise shows as rotationally spreading
constellation points;
d) Amplitude compression causes the corner points to
move towards the center.
In this simulation, an instrument called Discrete Time
Scatter Plot scope is employed to relay the constellation
diagram of the transmitted and received signals.
Figure 3. Use of Constellation Diagram in System Performance Analysis.

Figure 3. 64QAM Modulated Signal Constellation on Discrete Time Scatter Plot Scope.
2.8. Automatic code generation with Real-Time Workshop.
Real-Time workshop generates and executes stand-alone
C code for developing and testing algorithms modeled in
Simulink and embedded Matlab code. The resulting code can
be used for many real-time and non-real-time applications,
including simulation acceleration, rapid prototyping and
hardware-in-the loop testing. The generated code can be
tuned and monitored using simulink blocks and built-in
analysis capabilities, or run and interact with the code outside
the Matlab and simulink environment.
Key features of Real-Time workshop include:
• Generates ANSI C and C++ code and executables for
discrete, continuous or hybrid simulink models;
• Uses model blocks to incrementally generate and
build code for large applications;
• Supports simulink data dictionary features for integer,
floating point and fixed point data;
• Generates code for single-rate, multirate and
asynchronous models;
Supports single-tasking and multitasking operating
systems and bare-board (no operating system) environments;
• Performs code optimizations that improve code
execution speed;
• Provides capabilities for code customization and
legacy code generation;
• The generated code can be tuned and monitored
within or outside Simulink.
3. System Design
3.1. IEEE 802.11g Physical layer services
IEEE 802.11g PHY offers information transfer services to
the Data link control (DLC). For this purpose, it provides for
functions to map different DLC Protocol Data Unit (PDU)
trains into framing formats, called PHY bursts, appropriate
for transmitting and receiving management. IEEE 802.11g
PHY layer was conceived to offer link-adaptive data rates of
up to 54Mbps using Orthogonal Frequency Division
Multiplexing (OFDM) in the 2.4GHz ISM band. For
backward compatibility with the very popular IEEE 802.11b
(Wi-Fi), it also incorporates High Rate Direct Sequence
Spread Spectrum (HR-DSSS) technique for rates up to
11Mbps . Therefore PHY layer design of IEEE 802.11g
involves a parallel design of both OFDM and DSSS
transmitters and receivers and their appropriate management
logic.
IEEE 802.11g PHY Consist of two functions:
• Physical layer convergence function; Supported by
Physical Layer Convergence Procedure (PLCP) that
defines method of mapping MAC sub layer Protocol
Data Units (MPDU) into frame suitable for sending
and receiving user data and management information.
Also it enables MAC to operate at minimum
dependence on Physical media by simplifying PHY
service interface to MAC services.
• Physical Media Dependent (PMD) function that
produces methods for transmitting and receiving data
through the wireless medium.

3.2. DSSS Subsystem Design
IEEE 802.11g PHY DSSS subsystem is the same as IEEE
802.11b PHY. It is based on the principle of using codes to
spread a baseband signal over a wider bandwidth, similar to
what is obtainable in Code Division Multiple Access
(CDMA) systems. It supports four data rates: 1Mbps and
2Mbps (Low-Rate DSSS); 5.5Mbps and 11Mbps (High-Rate
DSSS). It consists of two major functions: spreading and
modulation. Other (ancillary) functions in the subsystem, like
Data Scrambling/Descrambling, Filtering, etc., have to do
with error management for better received data integrity. The
receiver performs the reverse of the functions of the
transmitter.
3.3. OFDM Subsystem Design
The IEEE 802.11g also specifies an OFDM PHY that
splits an information signal across 52 separate Sub-carriers to
provide transmission of data at rates of 6, 9, 12, 18, 24, 36,
48 or 54Mbps. In this mode, a pseudo binary sequence is sent
through the pilot sub- channels to prevent the generation of
spectral lines. The remaining 48 Subcarriers provide separate
wireless pathways for sending the information in a parallel
fashion [26].
3.4. OFDM Signal Representation
In an OFDM System, data is carried on multiple sub-
carriers. The modulation of sub-carriers is done directly in
the frequency domain using complex multiplication; the
resulting data are transformed into the time domain using the
IFFT at the transmitter and transformed back to frequency
domain using the FFT at the receiver. The number of points
of the IFFT/FFT used in a system depends on the number of
sub-carriers used [18]. In 802.11g system, the number of sub-
carriers used is 52, which translates to using a 64-point
IFFT/FFT.
The discrete-time representation of the signal using N
sub-carriers is given by the equation [18]:
∑
−
=
=
12/
2/
ej2ðK/Nn
)(/1)(
N
NK
ekXNnX

3.1
where X (k) is the complex modulation vector and n Є [-N/2,
N/2].
At the receiver side, the data is recovered by performing
an FFT on the received signal, i.e.
∑
−
=
=
12/
2/
ej2ðK/Nn
)(/1)(
N
NK
ekXNnX
3.2
where kЄ [-N/2, N/2].

Figure 4. OFDM Transmitter block diagram.
3.5. OFDM Transmitter Design.
The encoding of data into OFDM signals is as follows
[18]:
a) Generate the short training sequence and long training
sequence;
b) Generate the SIGNAL field bits, coding and
interleaving SIGNAL field bits, and map them into
frequency domain, insert pilots and transform into
time domain;
c) Prepend the SERVICE field, and add pad bits to the
octet stream and form the DATA;
d) Scramble and encode the DATA using convolutional
encoding and puncture to get higher rates and map
them into complex BPSK, QPSK, 16-QAM or 64-
QAM symbols followed by pilot insertion;
e) Transform from frequency domain to time domain and
add a cyclic prefix and concatenate the OFDM
symbols into a single time-domain signal.
Thus, an OFDM transmitter block diagram is as in
figure.3.1 below [26] [18]
The tasks of the physical layer blocks on the transmitter
side (fig. 4.6) will be discussed in detail in the following
sections. We will see by “reverse engineering” why certain
choices are made in the physical layer of IEEE 802.11g
system. This gives useful insight in the system for designing
an IEEE 802.11g receiver.
3.6. Forward Error Correction (FEC) Coding
Forward error Coding, or Channel Coding, is a method of
adding redundancy to the sent information so that it can be
transmitted over a noisy channel, and subsequently be
checked and corrected for errors that occurred in the
transmission. In IEEE 802.11g, convolution coding is used.
As earlier stated in Chapter 2, IEEE 802.11g operates a link-
adaptive rate up to 54Mbps. In the same way, the code rate
also varies. The code rate is defined as [17]
Input bit rate
RC
Output bit rate
= 3.3
The transmitter and receiver decide per transmission burst
what bit rate is actually used, depending on the link (channel)
characteristics. Table 4.4 [26] summarizes these.
Table 3.1. IEEE 802.11g Coding
Data
Rate
(Mbps)
Modulation Coding
Rate
(Rc)
Coded
Bits per
Subcarrier
Coded
bits per
OFDM
Symbol
Data
bits per
OFDM
Symbol
6 BPSK ½ 1 48 24
9 BPSK ¾ 1 48 36
12 QPSK ½ 2 96 48
18 QPSK ¾ 2 96 72
24 16-QAM ½ 4 192 96
36 16-QAM ¾ 4 192 144
48 16-QAM 2/3 6 288 192
54 64-QAM ¾ 6 288 216
Convolutional Codes are commonly specified by three
parameters: n, k and m, where n is the number of output bits,
k is the number of input bits and m is the number of memory
registers [37].
Figure 4. Convolutional Encoder [17].

3.7. Puncturing Convolution Codes
Puncturing is a very useful technique to generate
additional rates from a single convolutional code. The basic
idea behind puncturing is not to transmit some of the output
bits from the convolutional encoder, thus increasing the rate
of the codes. This increase in the rate decreases the free
distance of the code, but usually the resulting free distance is
very close to the optimum one that is achieved by specifically
designing a convolutional code for the punctured rate. The
receiver inserts dummy bits to replace the punctured bits in
the receiver, hence only one encoder/decoder pair is needed
to generate several different code rates. The encoder for a
punctured code can be fabricated using the original low-rate
convolutional encoder followed by a bit selector which
deletes specific code bits according to a given rule.
The puncture pattern is specified by the puncture vector
parameter in the mask. The puncture vector is a binary
column vector. A 1 indicates that the bit in the corresponding
position of the input vector is sent to the output vector, while
a 0 indicates that the bit is removed.
To create a rate ¾ code from the rate ½, constraint length
7 convolutional code, the optimal puncture vector is [1 1 0 1
1 0] ` (where the “` “after the vector indicates the transpose).
Bits in positions 3 and 6 are removed. Now for every 3 bits of
input, the punctured code generates 4 bits of output (as
opposed to the 6 bits produced before puncturing). This
makes the rate ¾.
4. System Implementation
Having explored the design details of IEEE 802.11g PHY
layer in the last chapter, this chapter presents the
implementation of these functional entities for the SDR
project. In this work, a three-step implementation approach is
employed, which includes:
• Creating a graphical model of the system using
essentially Digital Signal Processing (DSP) and
communication Blocksets in Matlab with the aid of
Simulink model editor;
• Performance evaluation of the simulated model;
• Generation of the software codes.
As earlier stated, IEEE 802.11g PHY consists of OFDM
and DSSS subsystems. OFDM is the major one, while DSSS
mode is only switched when the system is in any
environment that has IEEE 802.11b node or access point.
Since the major decision regarding the mode that the PHY
operates is taken at the data link layer, which is outside the
scope of this project, the two subsystems are implemented
separately.
4.1. Modeling of IEEE 802.11g OFDM PHY
The model depicts the time-independent mathematical
relationships between the system’s inputs, state and outputs
of various systems physical layer functional entities.
Simulink model editor offers a good environment for
achieving this. The different functional entities (blocks) are
sourced from their respective blocksets. Those that cannot be
sourced are created by defining the inputs, outputs and
appropriate mathematical relationships. The set parameters
for all the functional blocks are as generated at the design
stage in section 4. Table 4.1 below provides a summary of
the general parameters for the OFDM.
For the purpose of simulation, use is made of a Bernouli
Binary Generator. This block generates random binary
numbers using Bernouli distribution. 216 samples per time
3.8. Data Interleaving
Interleaving aims to distribute transmitted bits in time or
frequency or both to achieve desirable bit error distribution
after demodulation. The interleaver decorrelates the data and
spreads adjacent data over many subcarriers. All encoded bits
are interleaved by a block interleaver with a block size
corresponding to the number of bits in a single OFDM
symbol, NCBPS (288) [38]. The interleaver is defined by a
two-step permutation:
• Let k be the index of bits at the input, let i be the bit
index after this permutation and let NBPSC be the
number of bits mapped per OFDM subcarrier. The
first permutation is given by [17]
are used based on the standard, at 54Mbps (Table 4.2 refers).
Table 4.1. Global Parameters.
Parameters Value
Nsd: number of data subcarriers 48
Nsp: number of pilot subcarriers 4
Nfft: number of FFT subcarriers 64
Ncyclic: cyclic prefix 16
Viterbi Depth: Tradeback depth in the
viterbi decoder
34
OFDMSymbolDuration: Duration of
one OFDM symbol
4e-006
Puncture Vector [110110]
i = NBPSC (k mod 16) /16 + floor (k/1 (3.4)
With k = 0, 1 … NBPSC-1
• Let i be the bit index after the first permutation and let
j be the index after this permutation. The second
permutation is given by
j = S floor(s/i) + [I + NBPSC – floor (16i/NBPSC) mod S](3.5)
With i = 0, 1 … NBPSC-1 and S = max (NBPSC/2, 1).
Tx Signal 1
1
Rectangular QAM
Modulator
Baseband
Rectangular
QAM
Puncture
Puncture
OFDM
Transmitter
Normalize
Matrix
Interleaver
Matrix
Interleaver
General Block
Interleaver
General
Block
Interleaver
Convolutional
Encoder
Convolutional
Encoder
Bernoulli Binary
Generator
Bernoulli
Binary

Figure 5. OFDM transmitter Model.

Figure 6. OFDM Transmitter block details.
4.2. OFDM Transmitter
OFDM transmitter functional Model is as presented in
figure 5 below. The scrambler is conspicuously missing in
the model because the data source for this simulation makes
that unnecessary. However, this is only for the purpose of
simulation. Actual transmitter incorporates this
Bernoulli Binary
Generator
Bernoulli
Binary
Figure 7. Bernouli Binary Generator.
4.3. OFDM Receiver
The functional Model of OFDM receiver is as presented
in figure 6. The receiver functions to reverse the processes
that the signals undergo during transmission so as to retrieve
the original baseband signals (MPDU) for service to the data
link layer.
Viterbi Decoder
Viterbi Decoder
Unipolar to
Bipolar
Converter
Unipolar to
Bipolar
Converter
Rectangular QAM
Demodulator
Baseband
Rectangular
QAMOFDM
Receiver
pilots
Matrix
Deinterleaver
Matrix
Deinterleaver
Insert Zero
Insert Zero
General Block
Deinterleaver
General
Block
Deinterleaver
Denormalize

Figure 8. IEEE 802.11g OFDM PHY.
Out
1AWGN
In
1

Figure 4.4. OFDM Receiver functional model.
A detail of OFDM Receiver block is presented in fig. 4.5.
Figure 9. OFDM Receiver block details.
4.4. Transmission Channel Model Implementation
Since no system transmits data perfectly, in this modeling
process of IEEE 802.11g OFDM PHY, the effect of
imperfections of the transmission channel is taken care of by
using the Additive White Gaussian Noise (AWGN) channel
block. When the input signal is real, this block adds a real
Gaussian noise and produces a real output signal, likewise, it
The complete model (IEEE 802.11g OFDM PHY) is then
generated by combining as block.
This block is very important in assessing the performance
of the system under various noise levels and other
imperfections.
4.5. Performance Evaluation of the OFDM System
Having concluded the implementation of IEEE 802.11g
OFDM PHY model, it is time to perform some analysis in
order to assess the performance of the system. The approach
employed has to do with visual assessment of the
constellation diagrams of the received signals before
demodulation at different SNR (10dB, 15dB, 20dB, 25dB
and 50dB). This is then compared to a plot of Bit error rate
(BER) versus SNR already presented in figure 11 Random
Source block to generate the noise. The initial seed parameter
in this block initializes the noise generator.
performed on a similar OFDM system at the same data rate in
[12].
The constellation diagram of the transmitted signal after
modulation is as presented in fig. 12,13,14,15,16 and 17 adds
a complex Gaussian noise and produces a complex output
signal for a complex input. It inherits its sample time from
the input signal. It uses the signal processing blockset

Figure 11. IEEE 802.11g OFDM PHY.
Figure 12. Transmitted signal constellation.
Figure 13. The received 64 QAM signal constellation at SNR = 10db.
Figure 14. The received 64 QAM signal constellation diagram at SNR =
15db.
20db.

25db.
Figure 17. BER/SNR plot.
4.6. Modeling of IEEE 802.11g DSSS PHY
The same steps followed in the modeling of the OFDM
subsystem was also followed for DSSS modeling. The DSSS
PHY model is as presented in figure. 18 that follows.
Figure 18. IEEE 802.11g DSSS PHY model.
Figure 19. Real-Time Workshop Configuration Panel Window.

4.7. Generation of the prototype software for the system
Having designed, modeled, simulated and verified the
IEEE 802.11g PHY systems, the next stage is the generation
of the prototype software codes which, when implemented
with the other layers on a DSP or other general platforms will
fully implement the standard in software. As already
mentioned in Methodology, the software tool employed for
this is Real-Time workshop, from Mathworks incorporated.
There are several options available in Real-Time workshop
on code generation depending on the availability of support
tools and software.
It can:
• Generate a generic C or C++ code which can then be
targeted on any chosen platform. It neither builds the
executable code nor target it to any particular
platform;
• Generate the C or C++ codes and builds the
executable files but does not target it to any particular
platform. Availability of support software like Code
Composer Studio (CCS) can be of help in this regard.
• Generate the codes and builds the executable file
based on the chosen target but does not download the
file to the target; and
• Creates the codes, builds the executable based on a
chosen selected target. This of course needs support
hardware and software.
Due to uneasy access to the required hardware and
support software, this project is limited to generation of C
codes that when compiled and executed on any general
platform, will fully perform the functions of the physical
layer of IEEE 802.11g WLAN standard.
4.8. Software Generation Process
After modeling and simulation, with the model open and
in the current window, on the simulation menu,
‘configuration Parameters’ is clicked to bring out the panel in
the Real-Time Workshop Configuration Panel Window.
It is on this panel that all parameters and options are set
for the code generation process. After the configuration, the
‘Generate Code’ button is clicked and the software is
generated. The generated software is as presented in
appendices.
5. Conclusion
This thesis presented important issues for the design of
SDR-based wireless systems and exploration of this concept
by implementing the physical layer of IEEE 802.11g
standard. SDR is a promising technology that facilitates
development of multi-band, multi-service, multi-standard,
multi-feature handsets and future-proof network
infrastructure equipment. It is a revolutionary force of change
that will further push towards a wire-free society.
References
[1] Looking for 802.11g Wireless Internet Access information, definitions
and technology descriptions?
[2] List of WLAN Channels ^ "ARRLWeb: Part 97 - Amateur Radio
Service". American Radio Relay League.
http://www.arrl.org/FandES/field/regulations/news/part9 IEEE. ISBN
0-7381-5656-9.
[3] Official IEEE 802.11 working group project timelines". 2007
http://grouper.ieee.org/groups/802/11/Reports/802.11_Timelines.htm.
Retrieved on 2007-11-18.
[4] "How to: Migrate to 802.11n in the Enterprise".
nets.com/resources/tutorials/migrate_80211n.html. Retrieved on 2008-
10-08.
[5] http://www.wirevolution.com/2007/09/07/how-does-80211n-get-to-
600mbps/
[6] "Cuadro nacional de Atribución de Frecuencias CNAF". Secretaría
eEstadottp://www.mityc.es/Telecomunicaciones/Secciones/Espectro/c
naf. Retrieved on 2008-03-05.
[7] Evolution du régime d’autorisation pour les RLAN". French
Telecommunications Regulation Authority (ART).
http://www.arcep.fr/uploads/tx_gspublication/evol-rlan-250703.pdf.
Retrieved on 2008-10-26.
[8] Channel Deployment Issues for 2.4 GHz 802.11 WLANs". Cisco
Systems,Inc. Channel.html. Retrieved on 2007-02-07.
[9] Garcia Villegas, E.; et. al. (2007), "Effect of adjacent-channel
interference in IEEE 802.11 WLANs", CrownCom 2007., ICST &
IEEE
[10] 802.11 Technical Section". http://wifi.cs.st-
andrews.ac.uk/wififrame.html. Retrieved on 2008-12-15.
[11] Understanding 802.11 Frame Types". http://www.wi-
fiplanet.com/tutorials/article.php/1447501. Retrieved on 2008-12-14.

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