Design and Implementation of 64 Bit RISC Processor Using System on Chip (SOC)

1. Design and Implementation of 64 Bit RISC Processor Using System
on Chip (SOC)
Y. B. N. V. Bhaskar
Department of ECE
Sri Vasavi Engineering
College
Tadepalligudem,
Andhra Pradesh
D. Rajesh Setty
Associate Professor
Department of ECE
Sri Vasavi Engineering
College
Tadepalligudem, Andhra
Pradesh
Addanki Purna Ramesh
Associate Professor
Department Of ECE
Sri Vasavi Engg College
Tadepalligudem
A.P, India 534101
purnarameshaddanki@gmail.com
Abstract
In this paper, we present the design and
implementation of a 64-bit reduced instruction
set (RISC) processor with built-in-self test
(BIST) features.
A built-in self-test (BIST) or built-in test (BIT)
is a mechanism that permits a machine to test
itself. Key features of the design including its
architecture, data path, and instruction set are
presented. The design is implemented using
VERILOG and verification is done on IUS
(CADENCE) simulator. The proposed design
may find applications where automation and
control is required, say, in bottling plants and
control of robotic movements. Illustrations
highlight the typical use of our processor in
bottling plants using exhaustive simulations.
Future applications may include its use in
vending machines, ATMs, mobile phones, and
Portable gaming kits.
Keywords
RISC, BIST, BIT, VERILOG, IUS.
1. Introduction
In today‟s Integrated Circuits (ICs), Built-In-
Self Test (BIST) is becoming increasingly
important as designs become more and more
complicated. Keeping the structural fault
coverage high along with maintaining an
acceptable design overhead is critical. It is
important to achieve a high level of reliability
with minimum cost and time. It is with this
goal in mind that BIST has become a major
design consideration in Design-For-Testability
(DFT) methods.
BIST is beneficial in many ways: First, it can
reduce dependency on external Automatic Test
Equipment (ATE). In addition, BIST can
provide at speed, in system testing of the
Circuit-Under-Test (CUT). This is crucial to
the quality component of testing. Also, BIST
can overcome pin limitations due to packaging,
make efficient use of available extra chip area,
and provide more detailed information about
the faults present.
In our thesis, a 64 bit RISC processor with
limited functionality is designed with an
architecture that supports BIST. The processor
has been designed keeping in mind specific
applications where automation and control is
required, for example in bottling plants. The
proposed design is done by implementing
MICA (Minimal Instruction Set Computer
Architecture) architecture. The design is
implemented on Cadence simulator (IUS –
Intensive Unified Simulator) and programmed
using Verilog. Netlist has been generated by
using Encounter RTL compiler and Power
Analysis is implemented by using SOC (System
on Chip).
2. Implementation
The architecture of the ALU consists of two
parts, the Operation Architecture, which does
the actual operation of the ALU, and the
Testing Architecture, which comes into play
only during testing. The Operation
Architectures consists of a five units, 4-bit
Carry Look Ahead adder (CLA), and a 4-bit
AND, OR, XOR and INVERTER gates. There
is a PreCLA to prepare the inputs based on the
arithmetic operation to be done. There is a
MUX which uses the select pins to select one
of the results from the above five units. The
Testing Architecture has a ROM which has the
discovered test patterns stored in. There is an
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2. address decoder to select which of the test
patterns will be applied. There is a Test MUX,
which depending on the value on the Test
Mode pin will present the test pattern or the
actual inputs to be operated upon, to the
Operation Architecture.
The architecture and the data path for the
proposed design are shown Fig. 1 and 2,
respectively. TABLE 1 gives the salient
technical features of the proposed processor.
TABLE 2 provides detailed explanation of the
entire instruction set.
Figure 1: 64 Bit RISC Processor Architecture
Table 1: Salient f eatures o f the proposed d esign
Features of the proposed design
Architecture MICA
Instructions 33
Instruction register 32 bit
Address counter 32 bits
Data memory 64 bits
Data bus 64 bits
Address bus 32 bits
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3. Figure 2: Data path for 64-bit RISC Processor
Table 2: Instruction set for the 64-bit RISC Processor
S.No Instructions Description
1 ADD - Arithmetic Addition
ADD dest, src; Adds "src" to "dest" and replacing the
original contents of "dest". Both operands are binary.
2 IAND - Logical AND
AND dest, src; Performs a logical AND of the two
operands replacing the destination with the result.
3 SKIPZ – Skip on Zero skipz, Skips one clock cycle when data entered is zero.
4
LTR - Load Task Register
(286+ privileged)
LTR src; Loads the current task register with the value
specified in "src".
5
LSL - Load Segment Limit
(286+ protected)
LSL dest, src; Loads the segment limit of a selector into the
destination register if the selector is valid and visible at the
current privilege level. If loading is successful the Zero Flag
is set, otherwise it is cleared.
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4. 6
INOT - One's
Complement Negation
(Logical NOT)
NOT dest; Inverts the bits of the "dest" operand forming the
1s complement.
7
NEG
Two's Complement
Negation
NEG dest; Subtracts the destination from 0 and saves the 2s
complement of "dest" back into "dest".
8
POP
Pop Word off Stack
POP dest; Transfers word at the current stack top (SS: SP) to
the destination then increments SP by two to point to the
new stack top. CS is not a valid destination.
9
PUSH
Push Word onto Stack
PUSH src
PUSH immed (80188+ only); Decrements SP by the size
of the operand (two or four, byte values are sign extended)
and transfers one word from source to the top (SS: SP).
10
SETS
Set if Signed (386+)
SETS dest; Sets the byte in the operand to 1 if the Sign Flag
is set, otherwise sets the operand to 0.
11 ROL - Rotate Left
ROL dest, count; Rotates the bits in the destination to the
left count" times with all data pushed out the left side re-
entering on the right. The Carry Flag will contain the value
of the last bit rotated out.
12 ROR - Rotate Right
ROR dest, count; Rotates the bits in the destination to the
right "count" times with all data pushed out the right side re-
entering on the left. The Carry Flag will contain the value of
the last bit rotated out.
13
SAL/SHL
Shift Arithmetic Left /
Shift Logical
L
e
f
t
SAL dest, count
SHL dest, count; Shifts the destination left by "count" bits
with zeroes shifted in on right. The Carry Flag contains the
last bit shifted out.
14
SAR
Shift Arithmetic Right
SAR dest, count; Shifts the destination right by "count" bits
with the current sign bit replicated in the leftmost bit. The
Carry Flag contains the last bit shifted out.
15
SETC
Set if Carry (386+)
SETC dest; Sets the byte in the operand to 1 if the Carry Flag
is set, otherwise sets the operand to 0.
16
SETO - Set if Overflow
(386+)
SETO dest; Sets the byte in the operand to 1 if the Overflow
Flag is set, otherwise sets the operand to 0.
17
STC
Set Carry
STC; Sets the Carry Flag to 1.
18
STI
Set Interrupt Flag (Enable
Interrupts)
STI; Sets the Interrupt Flag to 1, which enables recognition of
all hardware, interrupts. If an interrupt is generated by a
hardware device, an End of Interrupt (EOI) must also be issued
to enable other hardware interrupts of the same or lower
priority.
19
SUB
Subtract
SUB dest, src; The source is subtracted from the destination
and the result is stored in the destination.
20
VERR
Verify Read
(286+protected)
VERR src; Verifies the specified segment selector is valid
and is readable at the current privilege level. If the segment
is readable, the Zero Flag is set, otherwise it is cleared.
21
CLC
Clear Carry
CLC; Clears the Carry Flag.
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5. 22
IXOR
Exclusive OR
XOR dest, src; Performs a bitwise exclusive OR of the
operands and returns the result in the destination
23
INAND
Logical NAND
Inand dest, sre; Performance a logical NAND of the two
operands replacing the destination with the result.
24
ADDI
Add Immediate
ADD dest, src; Adds "src" to "dest" and replacing the original
contents of "dest" Both operands are binary. It performs
immediate addition i.e. takes half clock cycle than in add.
Operation.
25
HLT
Halt CPU
HLT; Halts CPU until RESET line is activated, NMI or
maskable interrupt received. The CPU becomes dormant but
retains the current CS: IP for later restart.
26
SKIPN
Skip on Neg.
skipn; Skips one clock cycle when NEG instruction is
executed.
27
VERW
Verify Write
(286+ protected)
VERW src; Verifies the specified segment selector is valid
and is ratable at the current privilege level. If the segment is
writable, the Zero Flag is set, otherwise it is cleared.
28
CLR
Clear
clr; It clears every flag used in processor.
29
LD
Loads Data from Address
ld dest; Transfer data at the current address to the destination
then increments address to the point of new address.
30
ST
Stores Data to Address
st src; Transfers data from destination to the given address.
31
ISLL
Shift Logical Left
SAL dest, count
SHL dest, count; Shifts the destination left by "count" bits
with zeroes shifted in on right. The Carry Flag contains the
last bit shifted out.
32
JAL
Jump and Link
dest, src; Jumps the pointer from source to destination. Mainly
used in selection of the desired register at the moment
33
BR
Branch
br dest; Responsible for disabling the write enable for registers.
3.Applications
The proposed processor has been designed for
applications where control of movements and
automation is important. Example: Bottling
Plant. Bottles start filling from the right side
and boxes start to move from the left side. Here
four tracks of bottles are used simultaneously
therefore packing is made of four bottles.
When bottle reaches to the fourth position, box
moves to the first position. After that, bottle is
dropped in the box and hence, box moves one
position ahead. In this way, when box is at the
fifth position, signal „lb‟ is set to „1‟
indicating to lift the box.
.
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6. 4. Flow Chart
Figure 3: Flow chart for bottling plant
In the flow chart „a‟ shows position of bottle and „b‟ shows position of box
5. Algorithm
a=1, b=7, weight=0
loop a till a = 8
a = a+1; wait for 15 secs
If (a = 4) then
drop bottle in box
a = a-1;
End If;
If (a = 5) then
report error in bottle machine
End If;
End loop;
loop b till b = 5
b = b+1; wait till weight = 1;
If (b = 5) then
given signal to left box;
b = b-1;
End If;
If (b = 6) then
report error in packing machine
End if;
End loop;
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7. 6. Simulation Results
Figure 4: Simulation for 64-bit Risc Processor at 30 ns
Figure4 gives the simulated output obtained on the IUS (CADENCE) simulator.
Figure 5: Schematic diagram for 64-bit Risc Processor
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8. Figure 6: Simulation result for Addition operation
Figure 7: Detailed Timing report
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9. Figure 8: Instant power usage
Figure 9: Net power usage
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10. Figure 10: Probability Histogram
Figure 11: Report data path area
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11. Figure 12: Report RTL Power
7. Tools
IUS – Intensive Unified Simulator
IUS is used to determine
1. Logic of the design through waveforms
2. Timing analysis
3. Instantaneous power
Encounter RTL Compiler
1. This software is 52 version. By using RTL
compiler we can generate the NETLIST which
describes the number of gates, delays, power
consumption, etc.
2. By using RTL Compiler, we have designed
input/output padding for the RISC Processor
which will protect from power supply hazards.
SOC is used to determine post layout area of the
chip, clock tree synthesis, power considerations,
ordering of the pins, floor planning, etc.The
design is implemented by using all the software
which has TSMC (Taiwan Semi Conductor
Manufacturing Corporation) technology
libraries.
8. Conclusion
The 64 bit RISC Processor with an
instruction set has been designed. Each
instruction is designed in one clock cycle. The
design is verified through exhaustive simulation
and all the constraints like clock, power, delays,
etc. have been implemented using RTL
Compiler and SOC Encounter.
9. References
[1] Samuel O. Aletan, “An Overview of RISC
Architecture,” Proc. Symp. Applied Computing,
1992, pp. 11-12.
[2] Design and Implementation of a 64-bit RISC
Processor using VHDL, 2009 IEEE.
[3] D. Bhandarkar and D. W. Clark,
“Performance from Architecture: comparing a
RISC and a CISC with similar Hardware
Organization,” Proc. 4th International
Conference on Architectural Support for
Programming Languages and Operating
Systems, 1991, pp. 310-319.
[4] T. Marshall, “Worth the RISC,” The BYTE,
vol. 14, no. 2,1989, pp. 245-249.
[5] R. N. Noyce and M. E. Hoff, “A History of
Microprocessor Development at Intel,” IEEE
Micro, vol. 1, no. 1, 1981, pp. 8-21.
[6] J.L. Hennessy, "VLSI Processor
Architecture," IEEE Trans. Computers, vol. C-
33, no. 12, Dec. 1984, pp. 1221-1246.
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