1. PRAVEEN KUMAR NAGINENI
E-mail id :nvpraveen.nv8@gmail.com
Mobile No : +91-9738227164
OBJECTIVE
Seeking a position to utilize my skills and abilities in the Semiconductor Industry, which I have
developed in providing quality solutions, which are requirement focused. At the same time I would
like to update my knowledge base, which would further help me in being more productive.
SUMMARY
 1 year experience as a VLSI Front end ASIC Verification engineer.
 Currently working as a part of Verification Team (SV, UVM).
 Excellent troubleshooting and debugging skills.
 Developing functional verification plan, cover groups and cover Points.
 Developing randomized and directed test cases.
 Knowledge on OOPS concepts.
 Knowledge on UVM concepts.
 Knowledge on functional coverage.
 6 months internship in mavarik silicons.
EDUCATION
Qualification
Year of
Passing
Institution Board/University Percentage
B.Tech(ECE) 2015
Malineni Lakshmaiah
Engineering College
JNTU-KAKINADA 65%
INTERMEDIATE 2011 NRI junior college
Board of Intermediate
AP
77.6%
SSC 2009 Paparao public school Board Of SSC 74%
TECHNICALSKILLS
HDL’s skills HVL’s : Verilog, System Verilog.
Verification methodology : Universal Verification Methodology (UVM)
Programming languages : C.
Simulators : Questasim, Modelsim

2. Project#1
Title: Development of Verification Environment for CPRI PCS protocol
Environment: Verilog, System Verilog and UVM Methodology.
EDA Tools: Questasim.
Description:
 CPRI Subsystem is a single lane which supports different data rates using 32/40b scheme is in
compliant to CPRI standard V.6.1.
 32/40bencoding/decoding is achieved by cascading four 8/10b encoders/decoders (IEEE802.3–
Clause 36).
 It also has 20/40 bit interface to transmit and receive data to and from Serdes Layer
respectively.
Responsibilities:
 Responsible for complete Verification closure.
 Build environment from the scratch.
 Written test cases to cover all functional features.
 Debugged Failed test cases to root cause the issue.
Project# 2
Title: 1G MAC VIP verification.
Environment: Verilog, System Verilog and UVM Methodology.
EDA Tools: Questasim.
Description:
 Ethernet is layered protocol which spread across MAC and Physical Layer of seven layer OSI
model. It supports multiple data rates start from 10Mbps to 100Gbps.
 MAC IP has Application Layer interface which Receives and Transmits raw data to Upper Layer.
 Also has GMII interface which transmits and receives Ethernet Frames To/From PCS.
 It has AHB configuration interface, to configure the MAC for required functionality and to Read
the status from the Status registers.
Responsibilities:
 Involved in Build environment.
 Involved in Developing Application side BFM.
 Developed Scoreboard to model Ethernet frame from raw data and to check Ethernet frame data
integrity.
 Developed Functional coverage model to track the progress of the verification.
PROJECTS

3.  Written test cases to cover all functional features.
 Debugged Failed test cases to root cause the issue.
Project# 3
Title: 10G PCS BFM IMPLEMENTATION.
Environment: Verilog, System Verilog and UVM Methodology.
EDA Tools: QUESTA SIM.
Description:
 PCS VIP has XGMII interface to transmit and receive data from MAC Layer.
 It also has customizable interface to transmit and receive data to and from Serdes Layer
respectively.
 The key feature of these VIP is it will support both IP level and block level verification.
 During the IP level verification all the components in BFM transmitter and receiver path are
active.
 During the block level verification only selected components inside the BFM are active.
Role:
 Prepared Verification plan to implement the VIP.
 Involved in developing all the components inside the VIP using UVM and SV.
 Developed the agents which will drive the XGMII level data and PMA level data to the BFM
during the IP level verification.
 Developed the block level agent which will drive the respective interface level data to the
selected component in the BFM during the block level verification.
 Developed the clock generator block to supply the clocks for individual blocks in BFM.

 Good and Effective communication Skills
 Smart Working and committed to work.
 Good Interpersonal skills
Name : NAGINENI VENKATA PRAVEEN KUMAR
Father’s Name : N.V.KRISHNA RAO
Date of Birth : 14-08-1994
Sex : male
Marital status : Single
Nationality : Indian
Languages known : Telugu, English.
Permanent address : N.V.Praveen Kumar.
PERSONALDETAILS
STRENGTHS

4. S/o. N.V.Krishna rao,
kattavaripalem (vlg),
Kondapi(mdl),
Prakasam(dt), Andhra Pradesh - 523270
I hereby declare that the information furnished above is true to the best of my knowledge.
Yours sincerely
N.V.Praveen Kumar;
Place: Bangalore
DECLARATION