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Compute Express Link
(CXL) – Everything You
Ought To Know
*This presentation is the intellectual property of Logic Fruit Technologies . Any plagiarism or misuse is
punishable according to Indian Laws.
November 2022
What is Compute Express Link?
Compute Express Link (CXL), an open industry standard memory connection. It offers fast connectivity
between the many forms of memory utilized in modern data centres, including CPUs, TPUs, GPUs, and
other processor types.
2
Intensive workloads for CPUs and purpose built accelerators
are the focus of Compute Express Link, and a new open
interconnect standard enables efficient and coherent
memory access between a host and a device. Recently, the
Compute Express Link 1.0 specification was released along
with the announcement of a consortium to enable this new
standard.
To decide how to best leverage and incorporate this new
interconnect technology into their designs for AI, machine
learning, and cloud computing applications, system-on-chip
(SoC) designers need to be aware of some of the significant
Compute Express Link features that are described in this
article.
Compute Express Link Protocols & Standards
Communication protocols have made significant
advancements in the semiconductor sector.
The device-to-device performance required for
cloud-based workloads, artificial intelligence, and
machine learning applications is provided by the
PCIe Gen 5 (and Gen 6, whose version 1.0 is
scheduled for 2021) standard.
The central processing unit (CPU)-to-device and
CPU-to-memory communication provided by the
rapidly growing CXL standard enables next-
generation data centre performance.
3
CXL Vs. PCIe 5
CXL 2.0 adds protocols to PCIe 5.0’s physical and electrical interfaces that create coherency, streamline
the software stack, and preserve compatibility with current standards. To be more precise, CXL uses a
PCIe 5 feature that permits the usage of the physical PCIe layer by alternative protocols.
The default PCI Express 1.0 transfer speeds (2.5 GT/s) are used when a CXL-enabled accelerator is
plugged into an x16 slot to communicate with the host processor’s port.
Transaction protocols for Compute Express Link can only be used if both parties are CXL-compatible.
They function as PCIe devices otherwise.
The alignment of CXL and PCIe 5 allows both device classes to transfer data at 32 GT/s (Giga transfers
per second), or up to 64 GB/s in each direction over a 16-lane link, according to Chris Angelini of
VentureBeat.
Angelini also points out that the performance requirements of CXL probably drive the adoption of PCIe
6.0.
4
CXL 2.0
CXL has been one of the more intriguing connection standards in recent months.
Built on top of a PCIe physical basis, CXL is a connectivity standard intended to manage considerably more
than what PCIe can. In addition to serving as data transmission between hosts and devices, CXL has three
more branches to support: IO, Cache, and Memory.
5
How LFT can help with CXL
How LFT can help with CXL
LFT helps CXL in various ways, some of which are listed below:
 LFT has a proven track record on PCIe/CXL Physical Layer and thus, can provide support in the Physical
layer.
 LFT can provide support in architecting the various solutions of CXL.
 LFT will release a CXL IP during the first quarter of 2023.
6
To know more about Compute Express Link (CXL), see https://www.logic-fruit.com/blog/cxl/compute-
express-link-cxl/
Want to know more?
click on the below button, to learn more about
the Compute Express Link (CXL)
Learn More
TALK TO US TODAY
Sales@logic-fruit.com
www.logic-fruit.com

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Compute Express Link (CXL) – Everything You Ought To Know

  • 1. Compute Express Link (CXL) – Everything You Ought To Know *This presentation is the intellectual property of Logic Fruit Technologies . Any plagiarism or misuse is punishable according to Indian Laws. November 2022
  • 2. What is Compute Express Link? Compute Express Link (CXL), an open industry standard memory connection. It offers fast connectivity between the many forms of memory utilized in modern data centres, including CPUs, TPUs, GPUs, and other processor types. 2 Intensive workloads for CPUs and purpose built accelerators are the focus of Compute Express Link, and a new open interconnect standard enables efficient and coherent memory access between a host and a device. Recently, the Compute Express Link 1.0 specification was released along with the announcement of a consortium to enable this new standard. To decide how to best leverage and incorporate this new interconnect technology into their designs for AI, machine learning, and cloud computing applications, system-on-chip (SoC) designers need to be aware of some of the significant Compute Express Link features that are described in this article.
  • 3. Compute Express Link Protocols & Standards Communication protocols have made significant advancements in the semiconductor sector. The device-to-device performance required for cloud-based workloads, artificial intelligence, and machine learning applications is provided by the PCIe Gen 5 (and Gen 6, whose version 1.0 is scheduled for 2021) standard. The central processing unit (CPU)-to-device and CPU-to-memory communication provided by the rapidly growing CXL standard enables next- generation data centre performance. 3
  • 4. CXL Vs. PCIe 5 CXL 2.0 adds protocols to PCIe 5.0’s physical and electrical interfaces that create coherency, streamline the software stack, and preserve compatibility with current standards. To be more precise, CXL uses a PCIe 5 feature that permits the usage of the physical PCIe layer by alternative protocols. The default PCI Express 1.0 transfer speeds (2.5 GT/s) are used when a CXL-enabled accelerator is plugged into an x16 slot to communicate with the host processor’s port. Transaction protocols for Compute Express Link can only be used if both parties are CXL-compatible. They function as PCIe devices otherwise. The alignment of CXL and PCIe 5 allows both device classes to transfer data at 32 GT/s (Giga transfers per second), or up to 64 GB/s in each direction over a 16-lane link, according to Chris Angelini of VentureBeat. Angelini also points out that the performance requirements of CXL probably drive the adoption of PCIe 6.0. 4
  • 5. CXL 2.0 CXL has been one of the more intriguing connection standards in recent months. Built on top of a PCIe physical basis, CXL is a connectivity standard intended to manage considerably more than what PCIe can. In addition to serving as data transmission between hosts and devices, CXL has three more branches to support: IO, Cache, and Memory. 5
  • 6. How LFT can help with CXL How LFT can help with CXL LFT helps CXL in various ways, some of which are listed below:  LFT has a proven track record on PCIe/CXL Physical Layer and thus, can provide support in the Physical layer.  LFT can provide support in architecting the various solutions of CXL.  LFT will release a CXL IP during the first quarter of 2023. 6 To know more about Compute Express Link (CXL), see https://www.logic-fruit.com/blog/cxl/compute- express-link-cxl/
  • 7. Want to know more? click on the below button, to learn more about the Compute Express Link (CXL) Learn More TALK TO US TODAY Sales@logic-fruit.com www.logic-fruit.com