A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging

1. A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-
Digital Converter Based on Delay Wrapping and Averaging
ABSTRACT:
A high-resolution time-to-digital converter (TDC) implemented with field
programmable gate array (FPGA) based on delay wrapping and averaging is
presented. The fundamental idea is to pass a single clock through a series of delay
elements to generate multiple reference clocks with different phases for input time
quantization. Due to periodicity, those phases will be equivalently wrapped within
one reference clock period to achieve the required fine resolution. In practice, a
hybrid delay matrix is created to significantly reduce the required number of delay
cells. Multiple TDC cores are constructed for parallel measurements and then
exquisite routing control and averaging are applied to smooth out the large
quantization errors caused by the in homogeneity of the TDC delay lines for both
linearity and single-shot precision enhancement. To reduce the impact of
temperature sensitivity, a cancellation circuit is created to substantially reduce the
offset and confine the output difference within 2 LSB for the same input interval
over the full operation temperature range of FPGA. With such a fine resolution of
2.5 ps, the integral nonlinearity is measured to be from merely −2.98 to 3.23 LSB
and the corresponding rms resolution is 4.99–6.72 ps. The proposed TDC is tested

2. to be fully functional over 0 °C–50 °C ambient temperature range with extremely
low resolution variation. Its performance is even superior to many full-custom-
designed TDCs The proposed architecture of this paper analysis the logic size, area
and power consumption using Xilinx 14.2.
SOFTWARE IMPLEMENTATION:
 Modelsim
 Xilinx ISE