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1. HIGH-THROUGHPUT LDPC-DECODER ARCHITECTURE
USING EFFICIENT COMPARISON TECHNIQUES & DYNAMIC
MULTI-FRAME PROCESSING SCHEDULE
ABSTRACT:
This paper presents architecture of block-level-parallel layered decoder for irregular
LDPC code. It can be reconfigured to support various block lengths and code rates of IEEE
802.11n (WiFi) wireless-communication standard. We have proposed efficient comparison
techniques for both column and row layered schedule and rejection-based high-speed circuits to
compute the two minimum values from multiple inputs required for row layered processing of
hardware-friendly min-sum decoding algorithm. The results show good speed with lower area as
compared to state-of-the-art circuits. Additionally, this work proposes dynamic multi-frame
processing schedule which efficiently utilizes the layered-LDPC decoding with minimum
pipeline stages. The suggested LDPC-decoder architecture has been synthesized and post-layout
simulated in 90 nm-CMOS process. This decoder occupies 5.19mm2 area and supports multiple
code rates like 1/2, 2/3, 3/4 & 5/6 as well as block-lengths of 648, 1296 & 1944. At a clock
frequency of 336 MHz, the proposed LDPC-decoder has achieved better throughput of 5.13
Gbps and energy efficiency of 0.01 nJ/bits/iterations, as compared to the similar state-of-the-art
works.