Switch design

1. ECE2030
Introduction to Computer Engineering
Lecture 3: Switches and CMOS
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
Georgia TechGeorgia Tech

2. Basic Switch
• A pathpath exists when the Switch Control is closed
– If (Open) OUTPUT = unknown ; Switch is open (open (OFFOFF))
– Else OUTPUT = INPUT ; Switch is closedclosed (ON)
INPUT OUTPUT
Switch Control

3. The Analogy of A Transistor
Cross SectionCross Section
An N-Channel Metal-Oxide Semiconductor Field Effect Transistor (MOSFET)
INPUT OUTPUT
Switch Control (Gate)

4. Transistor Characteristics
• Cut-offCut-off Region
– Vgs – Vt ≤ 0
– No current (Ids) between drain and source
• LinearLinear (or Ohmic) Region
– 0 < Vds < Vgs – Vt
– Ids is a function of Vgs and Vds
– Ids = β*[(Vgs-Vt)*Vds – Vds*Vds/2]
• SaturationSaturation Region
– 0 < Vgs – Vt < Vds
– Ids is independent of Vds
– Ids = (β/2)*(Vgs-Vt)2
– β = process factor * (W/L)
• VtVt : Threshold voltage, a function of materials,
doping, insulator thickness, etc.
Gate
Drain
Source
Ids
Vds
Vgs
N-type MOS Transistor

5. Transistor Characteristics

6. Switches in Series
INPUT
OUTPUT
S1
S2
Truth Table
S1 S2 PATH?
OFF OFF
OFF ON
ON OFF
ON ON

7. Switches in Series
INPUT
OUTPUT
S1
S2
Truth Table (OFF/ON=0/1)
S1 S2 PATH?
OFF OFF NO
OFF ON NO
ON OFF NO
ON ON YES
What Function ??

8. Switches in Series
INPUT
OUTPUT
S1
S2
Truth Table (OFF/ON=0/1)
S1 S2 PATH?
0 0 0
Function = ??

9. Switches in Series
INPUT
OUTPUT
S1
S2
Truth Table (OFF/ON=0/1)
S1 S2 PATH?
0 0 0
0 1 0
Function = ??

10. 0
Switches in Series
INPUT
OUTPUT
S1
S2
Truth Table (OFF/ON=0/1)
S1 S2 PATH?
0 0 0
0 1 0
1 0 0
Function = ??

11. 1
Switches in Series
INPUT
OUTPUT
S1
S2
Truth Table (OFF/ON=0/1)
S1 S2 PATH?
0 0 0
0 1 0
1 0 0
1 1 1
Function = Logic ANDAND

12. 2
Switches in Parallel
INPUT
OUTPUT
S1
Truth Table
S1 S2 PATH?
OFF OFF NO
OFF ON YES
ON OFF YES
ON ON YES
S2

13. 3
Switches in Parallel
INPUT
OUTPUT
S1
Truth Table
S1 S2 PATH?
0 0 0
Function =??
S2

14. 4
Switches in Parallel
INPUT
OUTPUT
S1
Truth Table
S1 S2 PATH?
0 0 0
0 1 1
Function =??
S2

15. 5
Switches in Parallel
INPUT
OUTPUT
S1
Truth Table
S1 S2 PATH?
0 0 0
0 1 1
1 0 1
Function =??
S2

16. 6
Switches in Parallel
INPUT
OUTPUT
S1
Truth Table
S1 S2 PATH?
0 0 0
0 1 1
1 0 1
1 1 1
Function = Logic OROR
S2

17. 7
CMOS Transistor
• Complementary MOS
– P-channel MOS (pMOS)
– N-channel MOS (nMOS)
• pMOS
– P-type source and drain diffusions
– N substrate
– Mobility by holes
• nMOS
– N-type source and drain diffusions
– P substrate
– Mobility by electrons
Gate
Drain
Source
Gate
Source
Drain
pMOS
nMOS

18. 8
Pass Transistor using NMOS
• Assume capacitor (CL) is
initially discharged
• Gate=1, Vin=1
– CLbegins to conduct and
charges toward 1 (Vdd)
and stops at (Vdd-Vt)
– Signal is degraded
Gate=Vdd
Vin=Vdd
Vout
Ground
Load Capacitor
Vgs
I
Gate=Vdd
Vin=0
Vout=Vdd
Ground
Load Capacitor
Vgs
I
• Gate=1, Vin=0
– CLbegins to discharge
toward 0
–

19. 9
Transmission Degradation using
Pass Transistor
Vdd - VtVdd
Vdd (1)
Vdd - 2Vt
Vdd
Vdd
Vdd
Vout = Vdd- N*Vt
Still 1??

20. 0
CMOS Signal Transfer Property
Gate Path
0 Closed
1 Open
Gate
Drain
Source
Gate
Source
Drain
Gate Path
0 Open
1 Closed
pMOS
nMOS
• Transmits 1 well
• Transmits 0 poorly
• Transmits 0 well
• Transmits 1 poorly

21. 1
CMOS Transmission Gate
• Transmit signal from INPUT to OUTPUT when Gate is
closed
Gate (complementary of Gatecomplementary of Gate)
Source Drain
Gate
INPUT OUTPUT
Gate pMOS nMOS OUTPUT
0 OFF OFF ZZ
1 ON ON INPUT
ZZ : High-Impedance State,
consider the terminal is “floating”

22. 2
High Impedance
• When a path exists
– Impedance is low to
allow ample flow of
current
• When no path
– Impedance is high
allowing almost no
current flow between
two terminals
Gate=1
DrainSource
<< 10KΩ
>> 100MΩ
Closed
Gate=0
DrainSource
Open

23. 3
Transmission Gates
Gate = 1
0 0
Gate = 0
Transmit Logic 0
Gate = 1
1 1
Gate = 0
Transmit Logic 1

24. 4
Transmission Gate Symbol
Gate
Gate
INPUT OUTPUT
Gate
Gate
INPUT OUTPUT
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