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ENGR. RASHID FARID CHISHTI
LECTURER,DEE, FET, IIUI
CHISHTI@IIU.EDU.PK
WEEK 9
BEHAVIORAL MODELING
MOORE MACHINE
FPGA Based ...
www.iiu.edu.pk Sunday, May 17, 2015
Mealy Machine vs Moore Machine
2
module Moore_mdl (x,AB,CLK,RST); // Moore state diagram
input x,CLK,RST; output [1:0]AB; reg [1:0] PrState, NxtState;
para...
module test_Moore_Circuit;
reg x, CLK, RST; // inputs for circuit
wire [1:0] AB; // output from circuit
Moore_mdl mm1 (x, ...
www.iiu.edu.pk Sunday, May 17, 2015
Examples
5
Moore Machine
// Structural description of sequential circuit
module Moore_mdl (x, y, AB, CLK, RST);
input x, CLK, RST; output y; output...
// Stimulus for testing sequential circuit
module test_Moore_mdl;
reg x, CLK, RST; // inputs for circuit
wire y; wire [1:0...
module Moore_mdl (x,Y, AB, CLK,RST); // Moore state diagram
input x,CLK,RST; output [1:0]AB; output Y; reg [1:0] PrState, ...
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Fpga 09-behavioral-modeling-moore-machine

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Fpga 09-behavioral-modeling-moore-machine

  1. 1. ENGR. RASHID FARID CHISHTI LECTURER,DEE, FET, IIUI CHISHTI@IIU.EDU.PK WEEK 9 BEHAVIORAL MODELING MOORE MACHINE FPGA Based System Design Sunday, May 17, 2015 1 www.iiu.edu.pk
  2. 2. www.iiu.edu.pk Sunday, May 17, 2015 Mealy Machine vs Moore Machine 2
  3. 3. module Moore_mdl (x,AB,CLK,RST); // Moore state diagram input x,CLK,RST; output [1:0]AB; reg [1:0] PrState, NxtState; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @ (posedge CLK or negedge RST) // to handle reset and clock if (~RST) PrState = S0; // Initialize to state S0 else PrState = NxtState; // Clock operations always @ (PrState or x) // to Determine next state case (PrState) S0: if (~x) NxtState = S1; else NxtState = S0; S1: if (~x) NxtState = S3; else NxtState = S2; S2: if (~x) NxtState = S3; else NxtState = S2; S3: if (~x) NxtState = S0; else NxtState = S3; endcase assign AB = PrState; // to determine output endmodule www.iiu.edu.pk Sunday, May 17, 2015 Moore Model 3
  4. 4. module test_Moore_Circuit; reg x, CLK, RST; // inputs for circuit wire [1:0] AB; // output from circuit Moore_mdl mm1 (x, AB, CLK, RST); initial begin CLK = 0; repeat (14) #5 CLK = ~CLK; end initial begin x = 0; repeat (7) #10 x = ~ x; end initial begin RST = 1; #3 RST = 0; #3 RST = 1; end endmodule www.iiu.edu.pk Sunday, May 17, 2015 Test Bench 4
  5. 5. www.iiu.edu.pk Sunday, May 17, 2015 Examples 5 Moore Machine
  6. 6. // Structural description of sequential circuit module Moore_mdl (x, y, AB, CLK, RST); input x, CLK, RST; output y; output [1:0] AB; wire Ta, Tb, A, B; assign Ta = x & AB[0], Tb = x; //Flip-flip input equations assign y = AB[1] & AB[0]; //Output equation T_FF BF (AB[0], Tb, CLK, RST); // Instantiate T flip-flops T_FF AF (AB[1], Ta, CLK, RST); endmodule module T_FF (Q,T,CLK,RST); // T flip-flop output Q; input T,CLK,RST; reg Q; always @ (posedge CLK or negedge RST) if (~RST) Q = 1'b0; else Q = Q ^ T; endmodule www.iiu.edu.pk Sunday, May 17, 2015 Structured Programming 6
  7. 7. // Stimulus for testing sequential circuit module test_Moore_mdl; reg x, CLK, RST; // inputs for circuit wire y; wire [1:0] AB; // output from circuit Moore_mdl mm1 (x, y, AB, CLK, RST); initial begin RST = 1; #7 RST = 0; #3 RST = 1; end initial begin CLK = 0; repeat (20) #5 CLK = ~CLK; end initial begin x = 1; repeat (10) #10 x = ~ x; end endmodule www.iiu.edu.pk Sunday, May 17, 2015 Test Bench 7
  8. 8. module Moore_mdl (x,Y, AB, CLK,RST); // Moore state diagram input x,CLK,RST; output [1:0]AB; output Y; reg [1:0] PrState, NxtState; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @ (posedge CLK or negedge RST) // to handle reset and clock if (~RST) PrState = S0; // Initialize to state S0 else PrState = NxtState; // Clock operations always @ (PrState or x) // to Determine next state case (PrState) S0: if (x) NxtState = S1; else NxtState = S0; S1: if (x) NxtState = S2; else NxtState = S1; S2: if (x) NxtState = S3; else NxtState = S2; S3: if (x) NxtState = S0; else NxtState = S3; endcase assign AB = PrState; // to show state assign Y = AB[0] & AB[1]; // to show state endmodule www.iiu.edu.pk Sunday, May 17, 2015 Moore Machine: Behavioral Programming 8

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