Flipflop

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Flipflop

  1. 1. ECE 301 – Digital Electronics Flip-Flops and Registers (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
  2. 2. Spring 2011 ECE 301 - Digital Electronics 2 Flip-Flops (continued)
  3. 3. Spring 2011 ECE 301 - Digital Electronics 3 SR Flip-Flop ● The SR Flip-Flop has three inputs – Clock (Ck) --- denoted by the small arrowhead – Set (S) and Reset (R) ● Similar to an SR Latch – S = 1 sets the flip-flop (Q+ = 1) – R = 1 resets the flip-flop (Q+ = 0) ● Like the D Flip-Flop, the Q output of an SR Flip-Flop only changes in response to an active clock edge. – Positive edge-triggered – Negative edge-triggered
  4. 4. Spring 2011 ECE 301 - Digital Electronics 4 SR Flip-Flop S R Q Q+ 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 not 1 1 1 allowed }Q+ = Q Q+ = 0 Q+ = 1 set reset store } } positive edge-triggered SR Flip-Flop State change occurs after active Clock edge
  5. 5. Spring 2011 ECE 301 - Digital Electronics 5 SR Flip-Flop (master-slave) Enabled on opposite levels of the clock SR Latches
  6. 6. Spring 2011 ECE 301 - Digital Electronics 6 SR Flip-Flop: Timing Diagram
  7. 7. Spring 2011 ECE 301 - Digital Electronics 7 JK Flip-Flop ● The JK Flip-Flop has three inputs – Clock (Ck) --- denoted by the small arrowhead – J and K ● Similar to the SR Flip-Flop – J corresponds to S: J = 1 → Q+ = 1 – K corresponds to R: K = 1 → Q+ = 0 ● Different from the SR Flip-Flop in that the input combination J = 1, K = 1 is allowed. – J = K = 1 causes the Q output to toggle after an active clock edge.
  8. 8. Spring 2011 ECE 301 - Digital Electronics 8 JK Flip-Flop }Q+ = Q }Q+ = 0 }Q+ = 1 }Q+ = Q' set reset store toggle Q+ = J.Q' + K'.Q Characteristic Equation:
  9. 9. Spring 2011 ECE 301 - Digital Electronics 9 JK Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock
  10. 10. Spring 2011 ECE 301 - Digital Electronics 10 JK Flip-Flop: Timing Diagram
  11. 11. Spring 2011 ECE 301 - Digital Electronics 11 T Flip-Flop ● The Toggle (T) Flip-Flop has two inputs – Clock (Ck) --- denoted by the small arrowhead – Toggle (T) ● The T input controls the state change – when T = 0, the state does not change (Q+ = Q) – when T = 1, the state changes following an active clock edge (Q+ = Q') ● T Flip-Flops are often used in the design of counters.
  12. 12. Spring 2011 ECE 301 - Digital Electronics 12 T Flip-Flop Q+ = T.Q' + T'.Q = T xor Q Characteristic Equation:
  13. 13. Spring 2011 ECE 301 - Digital Electronics 13 T Flip-Flop: Timing Diagram
  14. 14. Spring 2011 ECE 301 - Digital Electronics 14 Building a T Flip-Flop
  15. 15. Spring 2011 ECE 301 - Digital Electronics 15 Asynchronous Control Signals
  16. 16. Spring 2011 ECE 301 - Digital Electronics 16 Asynchronous Control Signals: Timing Diagram
  17. 17. Spring 2011 ECE 301 - Digital Electronics 17 D FF with Clock Enable
  18. 18. Spring 2011 ECE 301 - Digital Electronics 18 Registers
  19. 19. Spring 2011 ECE 301 - Digital Electronics 19 Several D flip-flops may be grouped together with a common clock to form a register. Because each flip-flop can store one bit of information, a register with n D flip-flops can store n bits of information. A load signal can be ANDed with the clock to enable and disable loading the registers. A better approach is to use registers with clock enables if they are available. Registers
  20. 20. Spring 2011 ECE 301 - Digital Electronics 20 Register: 4 bits
  21. 21. Spring 2011 ECE 301 - Digital Electronics 21 Data Transfer between Registers ● Data transfer between registers is a common operation in computer (i.e. digital) systems. ● Multiple registers can be interconnected using tri-state buffers. ● Data can be transferred between two registers by enabling the proper tri-state buffer.
  22. 22. Spring 2011 ECE 301 - Digital Electronics 22 Data Transfer between Registers
  23. 23. Spring 2011 ECE 301 - Digital Electronics 23 Register with Tri-state Output
  24. 24. Spring 2011 ECE 301 - Digital Electronics 24 Data Transfer using Tri-state Bus
  25. 25. Spring 2011 ECE 301 - Digital Electronics 25 A shift register is a register in which binary data can be stored and shifted either left or right. The data is shifted according to the applied shift signal; often there is a left shift signal and a right shift signal. A shift register must be constructed using flip-flops (i.e. edge- triggered devices); it cannot be constructed using latches or gated-latches (i.e. level-sensitive devices). Shift Register
  26. 26. Spring 2011 ECE 301 - Digital Electronics 26 Shift Register: 4 bits
  27. 27. Spring 2011 ECE 301 - Digital Electronics 27 Shift Register (4 bits): Timing Diagram
  28. 28. Spring 2011 ECE 301 - Digital Electronics 28 8-bit SI SO Shift Register
  29. 29. Spring 2011 ECE 301 - Digital Electronics 29 4-bit PI PO Shift Register
  30. 30. Spring 2011 ECE 301 - Digital Electronics 30 4-bit PI PO Shift Register: Operation
  31. 31. Spring 2011 ECE 301 - Digital Electronics 31 Parallel Adder with Accumulator
  32. 32. Spring 2011 ECE 301 - Digital Electronics 32 In computer circuits, it is frequently desirable to store one number in a register (called an accumulator) and add a second number to it, leaving the result stored in the register. Parallel Adder with Accumulator
  33. 33. Spring 2011 ECE 301 - Digital Electronics 33 n-bit Parallel Adder with Accumulator
  34. 34. Spring 2011 ECE 301 - Digital Electronics 34 Before addition in the previous circuit can take place, the accumulator must be loaded with X. This can be accomplished in several ways. The easiest way is to first clear the accumulator using the asynchronous clear inputs on the flip-flops, and then put the X data on the Y inputs to the adder and add the accumulator in the normal way. Alternatively, we could add multiplexers at the accumulator inputs so that we could select either the Y input data or the adder output to load into the accumulator. Loading the Accumulator
  35. 35. Spring 2011 ECE 301 - Digital Electronics 35 Adder Cell with Multiplexer
  36. 36. Spring 2011 ECE 301 - Digital Electronics 36 Questions?

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