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Flipflop
1. ECE 301 – Digital Electronics
Flip-Flops and Registers
(Lecture #19)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th
Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
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Flip-Flops
(continued)
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SR Flip-Flop
● The SR Flip-Flop has three inputs
– Clock (Ck) --- denoted by the small arrowhead
– Set (S) and Reset (R)
● Similar to an SR Latch
– S = 1 sets the flip-flop (Q+
= 1)
– R = 1 resets the flip-flop (Q+
= 0)
● Like the D Flip-Flop, the Q output of an SR Flip-Flop
only changes in response to an active clock edge.
– Positive edge-triggered
– Negative edge-triggered
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SR Flip-Flop
S R Q Q+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 not
1 1 1 allowed
}Q+
= Q
Q+
= 0
Q+
= 1
set
reset
store
}
}
positive edge-triggered
SR Flip-Flop
State change occurs
after active Clock edge
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SR Flip-Flop (master-slave)
Enabled on opposite levels of the clock
SR Latches
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SR Flip-Flop: Timing Diagram
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JK Flip-Flop
● The JK Flip-Flop has three inputs
– Clock (Ck) --- denoted by the small arrowhead
– J and K
● Similar to the SR Flip-Flop
– J corresponds to S: J = 1 → Q+
= 1
– K corresponds to R: K = 1 → Q+
= 0
● Different from the SR Flip-Flop in that the input
combination J = 1, K = 1 is allowed.
– J = K = 1 causes the Q output to toggle after an
active clock edge.
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JK Flip-Flop
}Q+
= Q
}Q+
= 0
}Q+
= 1
}Q+
= Q'
set
reset
store
toggle
Q+
= J.Q' + K'.Q
Characteristic Equation:
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JK Flip-Flop (master-slave)
SR Latches
Enabled on opposite levels of the clock
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JK Flip-Flop: Timing Diagram
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T Flip-Flop
● The Toggle (T) Flip-Flop has two inputs
– Clock (Ck) --- denoted by the small arrowhead
– Toggle (T)
● The T input controls the state change
– when T = 0, the state does not change (Q+
= Q)
– when T = 1, the state changes following an active
clock edge (Q+
= Q')
● T Flip-Flops are often used in the design of counters.
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T Flip-Flop
Q+
= T.Q' + T'.Q = T xor Q
Characteristic Equation:
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T Flip-Flop: Timing Diagram
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Building a T Flip-Flop
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Asynchronous Control Signals
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Asynchronous Control Signals:
Timing Diagram
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D FF with Clock Enable
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Several D flip-flops may be grouped together with a common
clock to form a register. Because each flip-flop can store one
bit of information, a register with n D flip-flops can store n bits
of information.
A load signal can be ANDed with the clock to enable and
disable loading the registers.
A better approach is to use registers with clock enables if
they are available.
Registers
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Register: 4 bits
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Data Transfer between Registers
● Data transfer between registers is a common
operation in computer (i.e. digital) systems.
● Multiple registers can be interconnected using
tri-state buffers.
● Data can be transferred between two registers
by enabling the proper tri-state buffer.
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Data Transfer between Registers
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Register with Tri-state Output
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Data Transfer using Tri-state Bus
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A shift register is a register in which binary data can be stored
and shifted either left or right. The data is shifted according to
the applied shift signal; often there is a left shift signal and a
right shift signal.
A shift register must be constructed using flip-flops (i.e. edge-
triggered devices); it cannot be constructed using latches or
gated-latches (i.e. level-sensitive devices).
Shift Register
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Shift Register: 4 bits
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Shift Register (4 bits): Timing Diagram
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8-bit SI SO Shift Register
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4-bit PI PO Shift Register
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4-bit PI PO Shift Register: Operation
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Parallel Adder with Accumulator
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In computer circuits, it is frequently desirable to store one
number in a register (called an accumulator) and add a
second number to it, leaving the result stored in the register.
Parallel Adder with Accumulator
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n-bit Parallel Adder with Accumulator
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Before addition in the previous circuit can take place, the
accumulator must be loaded with X. This can be
accomplished in several ways. The easiest way is to first
clear the accumulator using the asynchronous clear inputs
on the flip-flops, and then put the X data on the Y inputs to
the adder and add the accumulator in the normal way.
Alternatively, we could add multiplexers at the accumulator
inputs so that we could select either the Y input data or the
adder output to load into the accumulator.
Loading the Accumulator
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Adder Cell with Multiplexer
