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Chip package system apache - publish version

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Chip package system apache - publish version

  1. 1. Chip-Package-System (CPS)Co-Design Verification<br />Ronen Stilkol, Apache Design Solutions <br />Chipex 2011 Track D: Power Management & Signal Integrity<br />
  2. 2. What is Chip-Package-System?<br />Chip-Package-System Sign-off<br />Power, Thermal, Timing, EMI<br />
  3. 3. Chip-Package-System (CPS)<br />vdd_d<br />vdd_a<br />gnd_d<br />gnd_a<br />Board<br />
  4. 4. Technology Impact on CPS Issues<br />65nm vs 45nm<br />45nm ,28nm vs 65nm <br />28nm : 65nm <br />65nm<br />45nm<br />45nm : 65nm <br />Buffer di/dt Ratio<br />Relative Decap<br />Relative ESR<br />Buffer size<br />Decap size<br />Decap is less effective at advanced technologies<br />Advanced technologies show more Di/Dt<br />One die modeling is critical for CPS<br />
  5. 5. Concurrent Chip-Package-System Design<br />Zin<br />Package<br />Board<br />Transient Analysis of entire system level PDN network<br />Traditional view of chip is black box or simplistic model<br />Signal Integrity analysis of high speed signals<br />Detail Model of Chip allow concurrent system-package-die SI&PI analysis<br />Impedance Analysis of entire system level PDN network<br />
  6. 6. Chip-Package-System (CPS)<br />1.8V<br />1.2V<br />VRM<br />CHIP 2<br />Package<br />Board<br />Board<br />Board<br />Board<br />Board<br />Board<br />
  7. 7. Chip-Package-System (CPS)<br />1.8V<br />1.2V<br />VRM<br />CHIP 2<br />Package<br />Board<br />Board<br />
  8. 8. Chip-Package-System (CPS)<br />1.8V<br />1.2V<br />Chip Power Model + Package Extraction+ PCB/Board Extraction<br />VRM<br />CHIP 2<br />Package<br />EMI Noise<br />Power Integrity<br />Thermal Integrity<br />Power Delivery Network Impedance<br />Cost Control (low cost market and/or high volume)<br />Board<br />Board<br />
  9. 9. Chip-Package-System (CPS)<br />AC Analysis<br />Dynamic Voltage Drop<br />Red: Chip + Pkg analysis<br />Green: Chip + Pkg+ PCB analysis<br />With Package Model<br />Without Package Model<br />Models of the Chip, Package and PCB are necessary<br /> for an accurate result.<br />
  10. 10. Chip-Package-System (CPS)<br />EMI/EMC Analysis<br />Package/PCB EMI Map<br />Chip Emissions<br />Necessary to model the noise source (Chip) and propagation medium (Package/PCB)<br />5th harmonic<br />2nd harmonic<br />SSO Timing Analysis<br />
  11. 11. Model-Based CPS Convergence<br />L Metal<br />R Metal<br />R Pkg<br />L PCB<br />R PCB<br />Leaf Tx<br />Global PDNview<br />VRM<br />C4 PG Bump<br />On die Decap<br />On Boarddecap<br />C Metal<br />C Pkg<br />SoC Designersview<br />PCB/Pkg RLC, <br />S parameter<br />L Metal<br />R Metal<br />Leaf Tx<br />C4 PG Bump<br />On die Decap<br />C Metal<br />PCB Designersview<br />CPM<br />R Pkg<br />L PCB<br />R PCB<br />VRM<br />C4 PG Bump<br />On Boarddecap<br />Chip Power Model<br />C Pkg<br />Only Common reference point<br />
  12. 12. Chip Power Model (CPM™)<br /><ul><li> Chip on-die Power Grid RLC</li></ul>Model creation<br /><ul><li> Transistor current/cap/ESR </li></ul>Package/BoardModel<br /><ul><li> Multi-domain, distributed model
  13. 13. DC to multi-GHz validity
  14. 14. Advanced chip excitation modes
  15. 15. Full chip correlation</li></ul>ASICVendors<br />System Houses<br />Chip PowerModel<br />Two sides, co-verification<br />
  16. 16. Chip Power Model (CPM)<br />CHIP DATA<br />Layout(Early to Sign-off)<br />Library<br />CHIP ANALYSIS<br />Dynamic VectorLess<br />Dynamic VCD<br />Static<br />Chip Power Model<br />Static (Iavg, R)<br />Frequency domain (RLC)<br />Time-domain (I(t), RLC)<br />Modes<br />
  17. 17. Chip Power Model (CPM)<br />PCB + Package<br />Pads/bumps (Power & Ground) need to be associated to its corresponding<br /><ul><li>Chip PDN RLC </li></ul> Physical model of chip layout<br /><ul><li>Transistor/cell current /cap/ESR </li></ul> Electrical model of chip layout<br />
  18. 18. Chip Power Model (CPM)<br />Each port (or bump) reflects the current flow associated with that port (or bump) reflecting the on-die activity<br />Parasitics are associated with every port (or bump)<br />Each port (or bump) are coupled with every other port<br />Active Current Signature<br />Passive RC Values<br />
  19. 19. Detailed Chip Power Model Advantage <br />Detailed Chip Power Model<br />Detailed Chip Power Model<br />Traditional DieModel<br />Traditional Die Model<br />Chip Power Model<br />Design<br />Layout<br />Library<br />Chip Current<br /><ul><li>RLC reduction: billions of parasitics to thousands of Spice elements
  20. 20. Distributed with full couplings</li></ul>Chip Parasitics<br />Single Lumped Model<br />
  21. 21. Chip Power Model : Parasitic Model Benefits<br />Traditional approaches to modeling the chip parasitics:<br /><ul><li>Spreadsheet based
  22. 22. Hand-calculated estimates</li></ul> Limited coverage <br /> Pooraccuracy, especially for large, multi-domain designs<br />CPM advantages<br /><ul><li> Accurate broadband response over wide frequency range
  23. 23. Captures all chip capacitive effects (PDN, device, signal net)
  24. 24. Resistive and inductive shielding of die capacitances
  25. 25. Spatially accurate</li></li></ul><li>Chip Power Model – Distribution Matters<br />mem<br />mem<br />mem<br />mem<br />mem<br />Top Level500MHz<br />Top Level<br />Top Level<br />Top Level<br />Top Level<br />mem<br />mem<br />mem<br />mem<br />mem<br />mem<br />mem<br />mem<br />mem<br />mem<br />CPU<br />1.6Ghz<br />ARM<br />ARM<br />ARM<br />ARM<br />PLLvictim<br />PLL<br />PLL<br />PLL<br />PLL<br />Ground C4 Bumps<br />+ Rdie/Cdie<br />Bumps above CPU<br />Which ground plane<br />fits your request best?<br />+ Rdie/Cdie<br />Bumps above Top<br />+ Rdie/Cdie<br />Bumps above Mem<br />
  26. 26. Noise in Power Delivery Network (PDN)<br />4 major noise signatures in PDN<br />High<br />Low<br />Mid<br />High frequency noise:<br />10’s GHz range<br />Die<br />Local<br />Low frequency noise:<br />MHz range<br />Board<br />Socket<br /> Package<br />Global<br />Mid frequency noise:<br />10’s MHz range<br />Package<br />Die<br />Global<br />Very low frequency noise:<br />kHz range<br />Voltage Regulator<br />Board L,C<br />Global Impact<br />Decaps ~ uFDecaps ~ nFDecap ~0.1pF<br />Chip-Package-Board PDN simulation<br />
  27. 27. Chip Power Model - Resonance Aware<br />Default chip simulation is activating all the clock frequencies<br />In Resonance Aware, CPM should focus on a specific stressing frequency<br />Digital Current<br />dB<br />Distributed energy<br />between frequencies<br />Constant Power Mode<br />FFT<br />time<br />freq<br />Digital Current<br />dB<br />More energy around<br />Resonance frequency<br />Resonance Aware Mode<br />FFT<br />time<br />freq<br />
  28. 28. When to Consider Resonance?<br />Die cap/unit area can be used to estimate total die capacitance<br />
  29. 29. Chip-Package-System Summary<br />Chip, package and system integrated Power and Signal integrity simulations,are essential for accurate modeling of the design using advanced processes<br /><ul><li>Chip, package co-verification is done on the chip side when a package model is integrated into the die simulation
  30. 30. Chip, package co-verification is done on the package and system side using a detailed chip model that is extracted from the complete die spatial and electrical data
  31. 31. Early analysis model of the chip is required for early convergence of the package and system design
  32. 32. Chip Power Model includes the required features to support : VRM, jitter, impedance, transient, and resonance analysis</li></li></ul><li>Thank You<br />

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