Vedic multipliers implementated using the Vedic mathematics as the basis.

1. VEDIC MULTIPLIERS
Dept. of Electronics and Communication Engineering
Presentation on

2. Presented By,
Gana T B [4SM14EC024]
Dept. of ECE, SJMIT.
Under the guidance of :
1. Smt. PUSHPA K G BE, M.Tech
Asst. Prof. Dept. of E&CE
2. Smt. TANUJA T BE, M.Tech
Asst. Prof. Dept. of E&CE

3. INTRODUCTION

4. o Vedic multipliers designed on the basis of vedic mathematics.
o Vedic mathematics has 16 main sutras and 13 sub sutras.
o The beauty of vedic mathematics is to reduce complex calculations into
simple one.
o In most of the digital signal processing applications, the critical operations
are multiplication and accumulation.
o The DSP functions extensively make use of the multiply-accumulate
(MAC) operation, for high performance digital signal processing system.
o The main motivation behind this work is to achieve high speed through
VLSI design and implementation of MAC unit architecture using
multipliers based on Vedic mathematics.

6. EXISTING METHOD!
PROPOSED METHOD?
How does it differ?

7. o The multipliers are the most important part of all digital signal
processors like in realizing many important functions such as Fast
Fourier transforms (FFT) and convolutions.
o Since a processor spends considerable amount of time in performing
multiplication, an improvement in multiplication speed can greatly
improve system performance.
o The delay associated with the array multiplier is the time taken by the
signals to propagate through the gates that form the multiplication array.
o Large booth arrays are required for high speed multiplication and
exponential operations which in turn require large partial sum and partial
carry registers. Thus the system becomes complex.

8. o Implementing the multiplier using vedic sutra increases the speed of the
multiplication.
o Implementing the reversible logic Urdhava Tiryakbhyam multiplier reduces
the area and hence the power dissipation.
o The “Urdhva Tiryagbhyam” sutra is a general multiplication formula
applicable to all cases of multiplication such as binary, hex, decimal and
octal.
o The Sanskrit word “Urdhva” means “Vertically” and “Tiryagbhyam” means
“crosswise”.
o This sutras shows how to handle multiplication of larger numbers by
breaking it into smaller sizes.

11. EXAMPLES OF
URDHWA
TRIYAKBHYAM
ALGORITHM

17. APPLICATIONS?
17

18. Image processing using vedic multipliers

19. Block diagram of proposed Image compression system

20. Vedic multiplier for FIR filter

21. Vedic DSP architecture

22. ADVANTAGES &
DISADVANTAGES

23.  Since the partial products and their sums are calculated in parallel,
the multiplier is independent of clock frequency of processor. Thus
the multiplier will require the same amount of time to calculate the
product and hence is independent of clock frequency.
 Vedic multiplier has less number of gates required for given 8 × 8,
16× 16... Multipliers hence power dissipation is very small hence low
power consumption i, e., power efficient.
 As the number of bits increases, gate delay and area increases very
slowly as compared to other multipliers. The numbers of devices
used in Vedic multiplier are less. Therefore it is time, space efficient.
 The main advantage is delay increases slowly as input bits increase.
 Vedic multiplier has greatest advantage as compared to other
multipliers over gate delays and regularity of structures.
 Highest speed among conventional multiplier.
 It has higher throughput operations.

24.  Due to Urdhva tiryakbhyam structure, the system suffers from a
carry propagation delay in case of large numbers.
 As the number of bits increases above 32 or 64 bits the propagation
delay in calculating RHS part of the algorithm also increases
significantly..

25. CONCLUSION

26. o This presentation presents a highly efficient method of multiplication –
“Urdhva Tiryakbhyam Sutra” based on Vedic mathematics.
o It gives us method for hierarchical multiplier design and clearly indicates
the computational advantages offered by Vedic methods.
o The computational path delay for proposed 8x8 bit Vedic multiplier is
found to be 21.679 ns.
o Hence our motivation to reduce delay is finely fulfilled. Therefore, we
observed that the Vedic multiplier is much more efficient than Array and
Booth multiplier in terms of execution time (speed).
o An awareness of Vedic mathematics can be effectively increased if it is
included in engineering education.

27. THANK YOU

28. QUESTIONS