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Fk3110791084

  1. 1. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084 High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics M.Nagaraju1, R.Surya Prakash2, B.Vijay Bhaskar3 1 M.Tech Student, Department of ECE, Avanthi’s St.Theressa Institute of Engg & Tech College, Garividi. 2 Assistant professor, Department of ECE, Avanthi’s St.Theressa Institute of Engg & Tech College, Garividi. 3 HOD,Associate professor.Department of ECE, Avanthi’s St.Theressa Institute of Engg &Tech College, Garividi .ABSTRACT: The main aim of the project is to improve transformation based implementation[2], bit-serialthe speed of the complex multiplier by using vedic multiplication using offset binary and distributedmathematics. This Vedic Mathematics is the arithmetic [3], the CORDIC (coordinate rotationname given to the ancient system of mathematics, digital computer) algorithm [4], the quadratic residueor, to be precise, a unique technique of number system(QRNS)[5],and recently, the redundantcalculations based on simple rules and principles, complex numbersystem (RCNS) [6]. at the expense ofwith which any mathematical problem can done three additions as compared to the direct methodwith the help of arithmetic, algebra, geometry or implementation. A left to right array [7] for the fasttrigonometry can be solved. Traditionally complex multiplication has been reported in 2005, and themultiplier provides less speed only, because it does method is not further extended for complexnot use Vedic Mathematics concept. By using multiplication. But, all the above techniques requireVedic Mathematics concept we can skip carry either large overhead for pre/postprocessing or longpropagation delay. The system is based on 16 latency.Vedic sutras, in which we are using one kind of In algorithmic and structural levels, a lot ofvedic sutra actually word-formulae describing multiplication techniques had been developed tonatural ways of solving a whole range of enhance the effciency of the multiplier; whichmathematical problems.The main design features encounters the reduction of the partial products and/orof the proposed system are the reconfigurability the methods for their partial products addition, but theand flexibility. The proposed system is design principle behind multiplication was same in all cases.using VHDL or Verilog HDL and is implemented Vedic Mathematics is the ancient system of Indianthrough Xilinx ISE 9.1i navigator or modelsim6.0 mathematics which has a unique technique ofsoftwares. calculations based on 16 Sutras (Formulae). "Urdhva- tiryakbyham" is a Sanskrit word means vertically andKewords: Complex Multiplier, Exponent crosswise formula is used for smaller numberDeterminant, High Speed Radix Selection Unit, multiplication. "Nihilam Navatascaramam Dasatah"Vedic Formulas. also a Sanskrit term indicating "all fom 9 and last fom 10", formula is used for large number multiplication 1. INTRODUCTION and subtraction. All these forulas are adopted fom Complex multiplication is of immense ancient Indian Vedic Mathematics. In this work weimportance in Digital Signal Processing (DSP) and formulate this mathematics for designing the complexImage Processing (IP). To implement the hardware multiplier architecture in transistor level wit two clearmodule of Discrete Fourier Transformation (DFT), goals in mind such as: i) Simplicity and modularityDiscrete Cosine Transforation (DCT), Discrete Sine multiplications for VLSI implementations and ii) TheTransformation (DST) and modem broadband elimination of carry propagation for rapid additionscommunications; large numbers of complex and subtractions.multipliers are required. Complex number Mehta et al. [9] have been proposed a multipliermultiplication is performed using four real number design using "Urdhva-tiryakbyham" sutras, whichmultiplications and two additions/ subtractions. In was adopted fom the Vedas. The formulation usingreal number processing, carry needs to be propagated this sutra is similar to the modem arrayfom the least signifcant bit (LSB) to the most multiplication, which also indicating the carrysignifcant bit (MSB) when binary partial products are propagation issues. A multiplier design usingadded [1]. Therefore, the addition and subtraction afer "Nikhilam Navatascaramam Dasatah" sutras has beenbinary multiplications limit the overall speed. Many reported by Tiwari et. al [10] in 2009, but he has notalterative method had so far been proposed for implemented the hadware module for multiplication.complex number multiplication [2-7] like algebraic That 1079 | P a g e
  2. 2. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084Multiplier implementation in the gate level (FPGA) which involve variations in both the metal andusing Vedic Mathematics has already been reported polysilicon layers.but to the best of our knowledge till date there is noreport on transistor level (ASIC) implementation of ASICs are usually classified into one of threesuch complex multiplier. By employing the Vedic categories: full-custom, semi-custom, and structured.mathematics, an N bit complex number multiplicationwas transformed into four multiplications for real and 3.VEDIC SUTRASimaginary terms of the final product. this sutra is used The gifs of the ancient Indian mathematics infor the multiplication purpose, with less number of the world history of mathematical science are not wellpartial products generation, in comparison with array recognized. The contributions of saint andbased multiplication. When compared with existing mathematician in the feld of number theory, Srimethods such as the direct method or the strength Bharati Krsna Thirthaji Maharaja, in the fon of Vedicreduction technique, our approach resulted not only in Sutras (formulas) [11] are signifcant for calculations.simplifed arithmetic operations, but also in a regular He had explored the mathematical potentials fromarraylike structure. The multiplier is fully Vedic primers and showed that the mathematicalparameterized, so any confguration of input and operations can be carried out mentally to produce fastoutput word-lengths could be elaborated. Transistor answers using the Sutras. In this paper we arelevel implementation for perfonance parameters such concentrating on "Urdhva-tiryakbyham", andas propagation delay, dynamic leakage power and "Nikhilam Navatascaramam Dasatah" formulas anddynamic switching power consumption calculation of other formulas are beyond the scope of this paper.the proposed method was calculated by Model simusing 90 nm standard CMOS technology and "Urdhva-tiryakbyham " Sutra:The meaning ofcompared with the other design like distributed. this sutra is "Vertically and crosswise" and it is applicable to all the multiplication operations. Fig. 1 2. ASIC represents the general multiplication procedure of the The term ASIC stands for application- 4x4 multiplication. This procedure is simply knownspecific integrated circuit. An ASIC is basically an as array multiplication technique [12]. It is an effcientintegrated circuit designed specifically for a special multiplication technique when the multiplier andpurpose or application. Strictly speaking, this also multiplicand lengths are small, but for the largerimplies that an ASIC is built only for one and only length multiplication this technique is not suitableone customer. An example of an ASIC is an IC because a large amount of carr propagation delays aredesigned for a specific line of cellular phones of a involved in these cases. To overcome this problem wecompany, whereby no other products can use it are describing Nikhilam sutra for calculating theexcept the cell phones belonging to that product line. multiplication of two larger numbers.The remarkableThe opposite of an ASIC is a standard product or system of Vedic maths was rediscovered from ancientgeneral purpose IC, such as a logic gate or a general Sanskrit texts early last century. The system is basedpurpose microcontroller, both of which can be used in on 16 sutras or aphorisms, such as: "by one more thanany electronic application by anybody of the complex the one before" and "all from nine and the last fromvalues 10". These describe natural processes in the mind and side from the nature of its application, an ASIC ways of solving a whole range of mathematicaldiffers from a standard product in the nature of its problems. For example, if we wished to subtract 564availability. from 1,000 we simply apply the sutra "all from nineThe intellectual property, design database, and and the last from 10". Each figure in 564 is subtracteddeployment of an ASIC is usually controlled by just a from nine and the last figure is subtracted from 10,single entity or company, which is generally the end- yielding 436.user of the ASIC too. Thus, an ASIC is proprietaryby nature and not available to the general public. Astandard product, on the other hand, is produced bythe manufacturer for sale to the generalpublic. Standard products are therefore readilyavailable for use by anybody for a wider range ofapplications. The first ASICs, known as uncommittedlogic array or ULAs, utilized gate arraytechnology. Having up to a few thousand gates, theywere customized by varying the mask for metalinterconnections. Thus, the functionality of such adevice can be varied by modifying which nodes in the This can easily be extended to solve problems such ascircuit are connected and which are not. Later 3,000 minus 467. We simply reduce the first figure inversions became more generalized, customization of 1080 | P a g e
  3. 3. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-10843,000 by one and then apply the sutra, to get the For the fast multiplication using Nikhilam sutra theanswer 2,533.We have had a lot of fun with this type bases of the multiplicand and the multiplier would beof sum, particularly when dealing with money same, (here we have considered different base) thusexamples, such as £10 take away £2. 36. Many of the the equation can be rewritten as hardwarechildren have described how they have challenged implementation of this mathematics is shown in Fig.their parents to races at home using many of the 2. The architecture can be decomposed into threeVedic techniques - and won. This particular method main subsections: (i) Radix Selection Unit (RSU) (ii)can also be expanded into a general method, dealing Exponentwith any subtraction sum.The sutra "vertically andcrosswise" has many uses. One very usefulapplication is helping children who are having troublewith their tables above 5x5. For example 7x8. 7 is 3below the base of 10, and 8 is 2 below the base of 10. The Block level architecture of RSU is shown in Fig. 3.RSU consists of three main subsections: (i) Exponent Determinant (ED), (ii) Mean Determinant (MD) and (iii) Comparator. n number bit from input X is fed to the ED block. The maximum power of X is extracted at the output which is again fed to shifter and the adder block.The whole approach of Vedic maths is suitable for The second input to the shifter is the (n+1) bitslow learners, as it is so simple and easy to use.The representation of decimal 1.If the maximum powersutra "vertically and crosswise" is often used in long of X from the ED unit is (n-1) then the output of themultiplication. Suppose we wish to multiply shifter is 2n-1. The adder unit is needed to increment32 by 44. We multiply vertically 2x4=8. the value of the maximum power of X by 1. TheThen we multiply crosswise and add the two results: second shifter is needed to generate the value of3x4+4x2=20, so put down 0 and carry 2. 2".Here n is the incremented value taken from theFinally we multiply vertically 3x4=12 and add the adder block. The Mean Determinant unit is requiredcarried 2 =14. Result: 1,408. We can extend this to compute the mean of (2n-1+2n). The Comparatormethod to deal with long multiplication of numbers of compares the actual input with the mean value of (2n-any size. The great advantage of this system is that 1 +2n). If the input is greater than the mean then 2n isthe answer can be obtained in one line and mentally. selected as the required radix. If the input is less thanBy the end of Year 8, I would expect all students to the mean then 2n-1 is selected as the radix. The selectbe able to do a "3 by 2" long multiplication in their input to the multiplexer block is taken from the outputheads. This gives enormous confidence to the pupils of the comparator.who lose their fear of numbers.The mathematicalexpression for the proposed algorithm is shownbelow. Broadly this algorithm is divided into threeparts. (i) Radix Selection Unit (ii) ExponentDeterminant (iii) Multiplier.Consider two n bitnumbers X and Y. kl and k2 are the exponent of Xand Y respectively. X and Y can be represented as: 1081 | P a g e
  4. 4. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084 decrementing and shifter also stops shifting operation. The output of the decrementer shows the integer part (exponent) of the number.B.Exponent Determinant: The hardwareimplementation of the exponent determinant is shownin Fig. 4.The integer part or exponent of the numberfrom the binary fixed point number can be obtained 4.COMPLUX MULTIPLIERby the maximum power of the radix. For the nonzero Complex multiplier design by using parallelinput, shifting operation is executed using parallel in adders and subtractors has been designed by Saha[I].parallel out (PIPO) shift registers. The number of Fig. 5 shows the direct method for implementation ofselect lines (in FigA it is denoted as S1, So) of the the complex multiplier design. In this paper complexPIPO shifter is chosen as per the binary representation multiplier design is done using Vedic Multipliers andof the number (N-1)IO. Shift pin is assigned in PIPO Vedic subtractors. Multiplication Algorithm Theshifter to check whether the number is to be shifted or Complex multiplier design and its functionality werenot (to initialize the operation Shift pin is initialized discussed in the previous chapters. Now this chapterto low). A decrementer [13] has been integrated in deals with the simulation and synthesis results of thethis architecture to follow the maximum power of the Complex multiplier. Here Modelsim tool is used inradix. A sequential searching procedure has been order to simulate the design and checks theimplemented here to search the first I starting from functionality of the design.the MSB side by using shifting technique. For an Nbit number, the value (N-I)1O is Above shows the basic steps involved in implementation. The initial design entry of may be VHDL, schematic or Boolean expression. Thefed to the input of decrementer. The decrementer is optimization of the Boolean expression will bedecremented based on a control signal which is carried out by considering area or speed. Ingenerated by the searched result. If the searched bit is technology mapping, the transformation of optimized0 then the control signal becomes low then Boolean expression to FPGA logic blocks, that is saiddecrementer start decrementing the input values. The to be as Slices. Here area and delay optimization willsearched bit is used as a controller of the decrementer. be taken place. During placement the algorithms areWhen the searched bit is I then the control signal used to place each block in FPGA array. Assigningbecomes high and the decrementer stops further the FPGA wire segments, which are programmable, 1082 | P a g e
  5. 5. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084to establish connections among FPGA blocks through A comparison between different architecture in termsrouting. The configuration of final chip is made in of propagation delay and dynamic switching powerprogramming unit. consumption arithmetic, parallel adder based implementation, and algebraic transformation based implementation. Once the functional verification is done, the design will be taken to the Xilinx tool for Synthesis process and the netlist file generation. The Appropriate test cases have been identified in order to test this modelled Complex multiplier design. Based on the identified values, the simulation results which describes the operation of the Complex multiplier design has been achieved. This proves that the modelled design works properly as per the process. Simulations Results:RTL Schematic: The RTL (Register Transfer Logic) Partial products Generators:can be viewed as black box after synthesize of designis made. It shows the inputs and outputs of thesystem. By double-clicking on the diagram we cansee gates, flip-flops and MUX. Figure :Simulation results for Partial product generator Booth Encoder: 5. SIMULATION RESULT ANALYSIS All the algorithm of this paper was simulatedand their functionality was examined by using SpiceSpectre. Performance parameters such as propagationdelay and power consumptions analysis of this paperusing standard 90nm CMOS technology. To evaluatethe performance parameters, we give the values of thecomputational effort using array multiplier and Vedicmultiplier. As shown, the application of the Vedicmethod for multiplication cuts the amount of thehardware as well as increases the performanceparameters such as propagation delay, dynamic Figure :Simulation results for Booth Encoderswitching power consumptions, and dynamic leakagepower consumptions. The performance parametersanalysis using array multiplication and Vedicmultiplication is shown in Table I. Input data is takenas a regular fashion for experimental purpose. Wehave kept our main concentration for reducing thepropagation delay, dynamic switching power anddynamic leakage power consumption and energydelay product. 1083 | P a g e
  6. 6. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084Simulation results for Complex Multiplier : process, the device utilization in the used device and package is shown above. Timing Summary:Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 28.239ns Maximum output required time after clock: 4.283ns Maximum combinational path delay: No path found 7.CONCLUSION In this paper we report on a novel complex number multiplier design based on the formulas of the ancient Indian Vedic Mathematics, highly suitable for 6.SYNTHESIS RESULT high speed complex arithmetic circuits which are The developed Complex multiplier design is having wide application in VLSI signal processing. simulated and verified their functionality. Once the The implementation was done in Spice spectre and functional verification is done, the RTL model is compared with the mostly used architecture like taken to the synthesis process using the Xilinx ISE distributed.The developed Complex Multiplier design tool. In synthesis process, the RTL model will be is modelled and is simulated using the Modelsim converted to the gate level netlist mapped to a tool.The simulation results are discussed by specific technology library. This Complex multiplier considering different cases.The RTL model is design can be synthesized on the family of Spartan synthesized using the Xilinx tool in Spartan 3E and 3E.Here in this Spartan 3E family, many different their synthesis results were discussed with the help of devices were available in the Xilinx ISE tool. In order generated reports. to synthesis this design the device named as “XC3S500E” has been chosen and the package as 8.REFERENCES “FG320” with the device speed such as “-4”. The 1. P. K. Saha, A. Banerjee, and A. Dandapat, design of Reversible Watermarking Algorithm is "High Speed Low Power Complex synthesized and its results were analyzed as follows. Multiplier Design Using Parallel Adders and Device utilization summary: Subtractors," International Journal on Electronic and Electrical Engineering, (/EEE), vol 07, no. II, pp 38-46, Dec. 2009. 2. R. E. Blahut, Fast Algorithms for Digital Signal Processing, Reading, MA: Addison- Wesley, 1987. 3. S. He, and M. Torkelson, "A pipelined bit- serial complex multiplier using distributed arithmetic," in proceedings IEEE International Symposium on Circuits and Systems, Seattle, WA, April 30-May-03, 1995,pp. 2313-2316. 4. J. E. VoIder, "The CORDIC trigonometric computing technique," IRE Trans. Electron. Comput, vol. EC-8, pp. 330-334, Sept. 1959. 5. R. Krishnan, G. A. Jullien, and W. C. Miller, This device utilization includes the following. "Complex digital  Logic Utilization  Logic Distribution  Total Gate count for the Design The device utilization summery is shown above in which its gives the details of number of devices used from the available devices and also represented in %. Hence as the result of the synthesis 1084 | P a g e

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