1. Eric A Foreman, PhD
1789 Main St, Fairfax, VT 05454
(802) 242-4712 / eaf@ericforeman.net / www.ericforeman.net
OBJECTIVE
To secure a challenging and rewarding position in an innovative organization that promotes growth, advances my technical
skills/leadership capabilities, and welcomes my creative contributions.
SKILLS
EDA Tools: IBM Design Automation Tools. Algorithm and integration development.
Software languages: Tcl, C++.
Leadership Skills: Significant leadership experience with a proven track record of driving innovation.
Team player who enjoys collaborating, inventing, and organizing cross-disciplinary teams.
Effective and persistent at overcoming obstacles both technical and organizational.
PROFESSIONAL EXPERIENCE
IBM Corporation, Essex Junction, VT February 2001 –Present
Senior R&D Engineer, Team Lead, and IBM Master Inventor
Field of Specialty / Job Scope
 Responsible for leading a team to develop timing methodologies for ALL IBM server designs.
 Deep understanding of timing, multi-corner/multi-mode timing, statistical timing, process variation, and all input/output
parts of a timing flow.
 Work with many teams (IP Development, EDA Tool Development, Spice Modeling Development, Design Teams, Test,
Research in order to create and support a timing methodology to be used in a construction flow from synthesis to checking.
 Successful motivator and mentor that maintains a fun and innovative environment. Demonstrate a positive, ethical, and
goal-oriented attitude while leading research and development across geographies and organizational boundaries to meet
business commitments.
 Chair several meetings to brainstorm and develop new ideas for potential patent IP and paper publication.
Highlighted Accomplishments
 Successfully rolled out an industry first statistical timing methodology in the 65nm node.
 Developed statistical timing methodologies for 45nm and 32 nm, and 14nm technology nodes.
 Invented and implemented a Dynamic Voltage Frequency Scaling (DVFS) methodology to maximize chip clock
performance across multiple workload conditions.
 Created a single statistical timing run for functional timing sign-off which accounts for process variation, environmental
variation, and transistor aging variation while considering first, second, and third order delay sensitivities. The single
timing run used in a multi-threaded environment saved considerable runtime as compared to the same processing resource
used for multiple parallel non-single timing runs.
 Created a voltage binning flow for reduced power while maintaining performance targets. The voltage binning flow
considers 2-bin and n-bin techniques, and uses patented techniques to reduce OCV variation when analyzing timing results
in bin specific process ranges.
 Created Multiple-VT family timing flow to account for manufacturing silicon process variation tracking and mis-tracking
using several types of correlation techniques.
 Created Voltage Island timing flows which account for unique macro placement as well as multi-Voltage Island tracking.
 Created timing methodology to handle within layer and layer-to-layer metal interconnect process variation. Identified ways
to reduce timing pessimism due to process variation through statistical techniques and modification of parasitic extraction.
 Created a first ever statistical timing model-to-hardware correlation timing flow which analyzed test site hardware and
compared back to the netlist timing flow results. The results were used to optimize timing models and flow and prevent
unnecessary guard banding.
 Worked with and supported design teams to successfully tape-out well over 100 designs.
 Developed and implemented multi-corner multi-mode variation-aware timing accounting for metal interconnect
manufacturing process variation for 90 nm technology.
 Developed and implemented a cross-talk on delay and glitch noise analysis methodology. Worked with many designs to
understand ways to reduce unnecessary degradation using patented filtering techniques. Worked with designers to help
automate several fix up and noise avoidance techniques.
 Created regression tests to maintain software quality while providing numerous incremental improvements.
 Developed a team that regularly patents, publishes, and drives significant innovation resulting in successful chip tape-outs
meeting performance, power, and area targets, IBM Corporate recognition for innovation, and significant IP licensing
revenue.

2. EDUCATION
PhD, Electrical and Computer Engineering,
Clarkson University, Potsdam, NY December-2011
MS, Electrical Engineering,
Boston University, Boston, MA January-2001
BS, Electrical Engineering, Minor, Mathematics,
Pennsylvania State University, University Park, PA May-1999
PATENTS/AWARDS
 58 Patents Granted / 13 Patents Pending
 25 Publications / publication and patent list available upon request.
 IBM Corporate Award May-2012: only 83 IBMers recognized for breakthrough technical achievement.
 IBM Master Inventor, Sept-2012: recognized for innovation leadership, mentorship, and contribution to IBM invention
process.
 IBM Nineteenth Patent Plateau
 IBM Patent Award Nov-2009: awarded to top 10% of IBM US patents issued
 IBM Patent Award Sept-2009
 IBM Patent Award Dec-2007
 Design Automation Conference (DAC) Best Poster Paper Honorable Mention July-2009
 Clarkson University Scholarship / Boston University Scholarship
 IEEE Senior Member
PROFESSIONAL ACTIVITIES
 IEEE Member for Vermont Green Mountain Section
 Co-chair for Penn State Silicon Happy Valley Engineering Conference 2015, 2016, 2017
 Member of Technical Program Committee for ISQED Symposium 2015, 2016
 Reviewer for Journal IEEE Trans. on Computer-Aided Design
 Reviewer for Design Automation Conference (DAC) 2013, 2014
 VLSI Metal Interconnect Conference (VMIC) Executive Committee 2008
 Board Member for Penn State Electrical Engineering Society
 Alumni Mentor for EE Students at Penn State University
 Member of the IBM Software Invention Review Board
 Chair of IBM Timing Methodology Journal Club
 Chair of IBM Timing Patent Development Group
References Available upon request