Resume of Engineer and Economist

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Apek Mulay
17602 17th St, Suite 102242, Tustin, CA 92780-7915
Ph. +1-2147640868, email:contact@ApekMulay.com
Quadra-lingual professional is actively looking to offer my expertise and services in Hi-
tech industry where I can use my education, professional skills and experience to make
positive contributions to your organization. I constantly learn new technologies and
explore new opportunities where I can utilize my broad experience to make positive
contributions to your organization.
Professional Experience
Business and Technology Consultant, Mulay's Consultancy Services [May'14-
Present]
 Working closely with end customers and provide satisfactory technical reports, providing an
in-depth engineering and business analysis.
 Working with other engineering teams and procurement teams to help procure the desired
tools for performing advanced level engineering jobs. Interaction with tool vendors for
Operation and Maintenance purposes.
 Experience with product sales and marketing, consulting, approaching new clients for
expansion of the business including government think tanks in High Tech sector.
 Experience with blogging for business, Giving technical and business presentations to
prospective clients for business growth, Handling business tax returns for business.
 Popular industry blogger on LinkedIn, Semi.org, EBN, The Economic Times, electronics.ca
publications, Truthout.org, EE Times as well as www.ApekMulay.com
Sr. Failure Analyst, Evans Analytical Group [June’13- April’14]
 Responsible for Analog, Digital and Mixed Signal IC failure analysis for EAG customers.
 Tool owner of Multiprobe AFM and deprocessing samples for nanoprobing
 Layer by layer deprocessing of digital and mixed signal units to identify root cause of failure
by exposing via and metal traces using a combination of parallel polishing, Chemical or wet
etch and RIE or dry etch methods for technology nodes up to 28 nm.
 Multi-tasking and ability to deliver quality results within the cycle time goals for EAG
customers.
 Experience with QFI Pulse IR, QFI Backside Light Emission Microscopy and XIVA, Curve
Trace, Phoenix X-Ray system, TDR, Curve Tracer.
 Responsibilities included electrical analysis, characterization, package integrity,
Decapsulation, Optical Inspection, Fault Isolation and Physical analysis.
Sr. Failure Analyst, Microtech Analytical Laboratories [March’12- May ‘13]
 Responsible for Digital, Analog and Mixed Signal IC failure analysis for all Microtech
customers.
 Reverse engineering of samples for customers to Investigate Patent infringements.
 Developing low K dielectric dry etch recipes on RIE (Reactive Ion Etch) for deprocessing
digital units of Advanced CMOS technology up to 45 nm.
 Layer by layer deprocessing of digital and mixed signal units to identify root cause of failure
by exposing via and metal traces using a combination of parallel polishing, Chemical or wet
etch and RIE or dry etch methods.

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 Multi-tasking and ability to deliver quality results within the cycle time goals for all Microtech
customers.
 Experience with Bench testing, Bench set-ups, Emission Microscopy, SEM, Micro-probing, X-
Ray, optical microscopy, Laser, Chemical etching, decapsulation.
 Competitive Analysis as requested by Microtech customers.
Texas Instruments Inc. [May'08-March'12]
Device Failure Analysis Engineer in Advanced CMOS Technology Development team
 Provided timely and accurate “Root cause” identification of Advanced CMOS technology
based digital failing units for WTBU like OMAP, Rapuyama, 8MSRAM etc.
 Supported the quality assurance system and technical activities.
 Demonstrated excellent interpersonal skills, experienced working in multiple discipline project
teams (Memory Fails, Non-Memory reliability fails, Nanoprobing, AFM Analysis, Next
generation tool evaluation) and strong project management skills.
 Responsible for Physical Failure Analysis (PFA) on WTBU units to identify root cause of
failures.
 Performing nano-probing on Advanced CMOS technology devices to identify root cause
failures up to 28 nm technology node. Also capable of nanoprobing 28 nm HD.1234 6T
SRAM bit cell (Smallest 28nm 6T SRAM bit cell in entire semiconductor industry).
 Perform Electrical Fault isolation during deprocessing using SEM, Optical microscopes, laser
marker, Zyvex D-Nanoprober, K&W Nanoprober and Veeco AFM.
 Played Key role in evaluation of next generation Nanoprober to be procured for Texas
Instruments for performing failure analysis for 28nm and smaller technology node transistors.
 Participated in International symposiums and shared knowledge with co-workers on
advances in semiconductor industry for failure analysis of advanced transistor devices.
 Support PFA on package level Failure Analysis using backside prep using Allied High Tech
Polisher, Hitachi M 4000 Ion Milling tool as and when required by team.
 Contributing to Texas Instruments patents. Filed a Patent at Texas Instruments titled “Surface
Imaging with Materials Identified by Colors".
Dallas Device Analysis Operation, Texas Instruments Inc., Dallas, TX
 Provided timely and accurate “Root cause” identification of Analog Automotive failing units.
 Supported the quality assurance system and technical activities. Interaction with Analog
Design engineers to fix any circuit design issues resulting in failure of ICs.
 Frequently interacted with outside customers and functional peer groups at engineering
levels.
 Performed operational tests and fault isolation on integrated circuits which includes
experience with ATE, curve trace, micro-probing, light emission microscopy, liquid crystal.
 CSAM, XRAY,FIB, SEM and deprocessing techniques.
 Performed failure analysis on BiCMOS/CMOS/Bipolar precision analog ICs using electrical
and physical analysis techniques.
 Served as customer’s advocate inside to drive compliance with all customer quality and
reliability requirements.
 Demonstrated excellent interpersonal skills, experienced working in multiple discipline project
teams, customer interface roles and strong project management skills.
Failure Analysis Engineer (May’06 – May’08), Qualcomm Inc., San Diego, CA
 Gained experience with new silicon debugs, Qualification failures and yield enhancement on
Digital, RF Analog and Mixed signal ICs
 Gained experience working with in chemical operations lab. I have completed reverse

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engineering and de-processing for mixed signal, RF and digital products for 130 nm, 90nm
and 65 nm technologies.
 Hands on work with RIE and Plasma de-layering techniques w.r.t. developing skeleton etch
recipe and other recipes, delineation stains for cross-sections and planar views.
 Gained experience with analytical tools like optical microscopy, Scanning Electron
Microscopes (SEM), Laser Scanning Microscopes (LSM) techniques and Photon Emission
Microscope (PEM), Atomic Force Probe (AFP), Time Domain Reflectometer (TDR)
 Developed understanding of design for debug, digital/analog test methodologies and circuit
analysis skills.
 Proficient in making optimum use of Linux, UNIX and Windows environment.
 Hands on experience with lab test equipment (o-scopes, multi-meter, parametric analyzers,
logic analyzers), Automated Test Equipment (ATE).
 Interacted with RF, Analog, Mixed signal and power management design teams to ensure
robust circuit design during new product development cycles which include identifying design
and layout routing issues in front end as well as backend of the IC.
 Interacted with reliability engineering team in order to identify root cause of early and wear
out failures for QUALCOMM products
 Prepared detailed FA/RMA reports and making them available to the product engineering and
customer quality engineering teams.
Co-op (September’05 – Dec’05), X-Fab Texas Inc., Lubbock TX
Project: “Improving the Reliability of Tungsten Plug VIA for 0.6 μ BiCMOS and CMOS
Technology”
 Researched cost effective solutions to achieve maximum yield, quality and reliability
 Designed Experiments (DoE) and performed the designed experiments to improve process
and multiprobe yield, troubleshooting routings (process flows) and experimented recipes to
maximize process yields.
 Analyzed SEM, Passive Voltage contrast measurements, FIB cross-sections and Wafer data
Statistics.
 Prepared Special Work Requests (SWRs), worked closely with process engineers, product
engineers, test engineers and failure analysts at X-Fab (Lubbock) and X-Fab (Erfurt) to solve
problems and coordinate activities amongst cross-functional teams. Also managed the
assigned project.
 Saved a lot of money for X-Fab Texas by providing solution to improve the reliability of
stacked and non-stacked tungsten plug via with available set of equipments.
 Justified the need to invest of some additional tools that need to be purchased by X-Fab in
order to improve the yield of tungsten plug vias.
Engineer (August’02 – August’04), Reliance Infocomm, Navi Mumbai, India
 Technology evaluation, Validation, Acceptance Test and Quality Review activities at
Reliance.
 Operation and Maintenance activities for Ericsson ILT switch, Acceptance Testing and
validation activity
 Co-ordinated and managed the Quality review activities of transit network of 23 Ericsson
AXE-10 ILT.
 Participated in standardization activities in wire line team, standardization team and VoIP
team.
Education
MS in Electrical Engineering, Texas Tech University, Lubbock, TX. CGPA:3.63/4.0 BE
in Electronics Engineering, University of Mumbai, India. Rank in Inst.: 3rd/120 BE
B.E. Project @ Emerson Network Power India Pvt. Ltd.- ‘Design of DC power-supplies paralleling

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for equal current sharing’
MS Coursework
 Design and Analysis of Integrated Circuits (B+) - Designing schematics of Analog ICs
(Transistors, Capacitors and Transformers) , verifying DRC in layout, Simulating the circuit
which include parasitic extraction, timing verification.
 System modeling and simulation (A)
 Introduction to semiconductor processing (A)
 Advanced semiconductor processing (A)
 Physics of Solid state electronic devices (A+)
 Engineering Analysis (A)
 Computer Aided Circuit Analysis (A)
 Telecommunication Networks (B)
Technical Skills
Circuit design, simulation and layout packages – Cadence design suite, Catena LAYED,
Matlab & Simulink, PSPICE, Knights database.
Tools & Test Equipments – Karl Suss probe station, Reichert-Jung Polyvar Met, 93K
Tester, Hypervision and IREM-II Photon Emission microscopes, curve-tracer, Optical
microscopes, Hitachi Scanning Electron Microscope (SEM) S-4800, p-lapping T-tool,
Decapsulator, pico-probes, Multiprobe Atomic force Probe (AFP) MP1 and MP2, Hitachi TM-
100 Tabletop SEM, B1500A parametric Analyzer, SIRUS Reactive Ion Etcher (RIE), Trion
Reactive Ion Etch (RIE), Energy Dispersive X-Ray (EDAX) analyzer, Carbon coater, Agilent
Time Domain Reflectometer, UTI Multitrace system 625, Daye XD7600NT X-ray, SONIX
Scanning Acoustic Microscope, Tektronix 1180C digital sampling Oscilloscope, Yamato
DKN600 constant temperature oven, FEI FIB 800, FEI Dual beam 835, Hamamatsu Photon
Emission Microscope, S-4700 Scanning Electron Microscope, Fiber-Lite M1-150 High
intensity illuminator, Leica Microscope, Navitar 150 Illuminator, Sirus RFX600A Reactive Ion
Etch, Nisene Jet-Etcher, Buehler Ecomet 3 grinder-Polisher, Allied Multiprep polisher,
chemical and mechanical tools for failure analysis, Zyvex D-Nanoprober, K&W Nanoprober,
Veeco AFM, Bruker Icon AFM and Multiprobe AFP I and II, Hitachi M4000 Ion Milling Tool,
JSM -6500F Scanning Electron Microscope, RKD engineering Elite Etch, Digit Concept
Sesame 500, Nanomex SEM, Alessi REL-4800 Microprober, Sonix Scanning Acoustic
Microscope, Semicaps SPEMS 1350 PEM, QFI Pulse IR, QFI Backside Light Emission
Microscopy and XIVA, Phoenix X-Ray system.
Semiconductor fabrication tools – Canon PLAF-01 Mask Aligner, Dektak 3030 Surface
Profilometer, THERMO e-Gun.
Calibration and measurement tools and softwares – Keithley 2400 & 4200 semiconductor
parameter analyzer, HP4284A precision LCR meter, HP 4156B Precision Semiconductor
parameter analyzer, Multiscan II and Multiscan III software.
Semiconductor Industry skills – Design of Experiments (DoE), Statistical Process Control
(SPC), Process Integration, Failure Analysis, Customer Communication,Product engineering,
Characterization and Testing, Tool evaluation, etc.
Linguistic Skills (Read, Write, Speak)- English, Mandarin, Hindi, Marathi, Sanskrit
Honors and Affiliations
Professional Memberships:

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A valued member of EDFAS (Electronic Devices Failure Analysis Society) from 2006- Present.
A valued member of IEEE from 1999-2006.
Member of Semi.org since 2014.
Honors:
1. Member of “Failure Analysis Process” peer review committee at International Symposium
for Testing and Failure Analysis (ISTFA) 2008.
2. Chair person of “System Level Failure Analysis” session at ISTFA 2009.
3. Chair person of “Board and System Level Failure Analysis” session at ISTFA 2010.
4. Received Patent Reward from Texas Instruments for filing a Patent with USPTO on
"Surface Imaging using AFM with Materials Identified with colors"
5. Became a permanent resident of US under category of foreign nationals with their extra-
ordinary abilities in science and technologies.
6. Author of two books covering the macroeconomics of global semiconductor industry
entitled 'Mass Capitalism : A Blueprint for Economic Revival' and 'Sustaining Moore's
Law: Uncertainty Leading to a Certainty of IoT Revolution'.
Excellent professional References available upon request