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Apek Mulay resume


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Resume updated as of 17 May 2017

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Apek Mulay resume

  1. 1. Apek Mulay 657-235-7333;; EDUCATION The University of Texas at Dallas June 2018 M.S., Business Analytics GPA 4.00 Texas Tech University May 2006 M.S., Electrical Engineering GPA 3.63 University of Mumbai, INDIA June 2002 B.E., Electronics Engineering GPA 4.00 BUSINESS EXPERIENCE Co-operative Internship in Business Analytics, Intellisoft Technologies, Irving, TX May 2017 – Present Business and Technology Consultant, Mulay’s Consultancy Services, Tustin, CA May 2014 – Dec 2016 • Researched and analyzed the technology and business aspects of global semiconductor industry and pioneered in authoring 4 books on macroeconomics of semiconductor business with reputed publications to make the technological progress and the resulting economic progress both sustainable and profitable. • Conceptualized and published 150+ thought leadership pieces with reputed trade publications such as, EBN, The Economic Times,, Military & Aerospace Electronics (MA&E) magazine, Semiwiki, Financial Worldwide Magazine, NaSPA Magazine, LinkedIn and • Strategized an approach for ‘Make in India’ policy by evaluating macroeconomic parameters and provided consultancy to the think tank with Government of India. Also, invited by Indian media for Analysis. • Developed and implemented a low-cost start-up business model by means of collaboration with four other business professionals. Oversaw the implementation, negotiated better wholesale rates, Catalogued products, Contracted rates for shipping and standardized process flow as founder of Sr. Failure Analyst, Evans Analytical Group (EAG), Irvine, CA June 2013 – April 2014 • Evaluated complex root cause of failure for Broadcom Inc. Integrated Circuits (ICs). Troubleshot Multiprobe Inc. MP 1 Nanoprober and instituted that tool for an effective use in the laboratory. • Facilitated sample preparation on EAG customer samples that need to be nanoprobe by Multiprobe Inc. Developed new RIE etch recipes on Advanced CMOS technology samples for low-k dielectrics. • Pioneered Micro-probing with 8-probe needles on bench set-up with my experience with a nanoprober. Sr. Failure Analyst, Microtech Analytical Laboratories(MAL), Plano, TX April 2012 – May 2013 • Secured a lot of business from Texas Instruments Inc. in their process of shutting down Houston FA Lab (HDAO) and moving its operations to Dallas, TX. Improved the quality of HDAO products with available set of tools (to perform reverse engineering) at Microtech Laboratories. • Developed low-k and ultralow-K dielectric etch recipes with Trion Reactive Ion Etch (RIE). Broadened my engineering skillset by performing circuit analysis on analog and mixed signal devices, package level failure analysis for several Microtech customers such as Texas Instruments Inc., NVIDIA Inc., etc. • Performed reverse engineering to investigate patent infringement cases for MAL Customers. • Trained junior engineers at MAL on advanced CMOS deprocessing, Competitive analysis, etc. Failure Analyst, Texas Instruments Inc., Dallas, TX May 2008 – March 2012 • Increased revenue for Texas Instruments Inc. by being appreciated by DDAO management as one of the most productive employees in automotive team. Devised better processes to meet rigorous cycle time pressures to help achieve 0% Defective Parts Per Million (DPPM) goal of Texas Instruments Inc. Quality department. • At Advanced CMOS Technology Development team at Texas Instruments Inc., I evaluated and managed the project of evaluating the investment of 1.5 million USD needed to procure the next generation nanoprober for performing Nanoprobing at 28 nm and smaller technology nodes at Texas Instruments Inc. • Contributed to patent portfolio of Texas Instrument Inc. and awarded patent award by Texas Instruments Inc.
  2. 2. • Reviewed Papers and chaired technical sessions at ISTFA 2009 and 2010 Symposiums. Failure Analyst, Qualcomm Inc., San Diego, CA May 2006 – March 2008 • Performed Nanoprobing using Multiprobe MP1 Nanoprober on 65 nm products for Qualcomm’s new product development team. Tool owner for MP1 Nanoprober at Qualcomm Inc. • Improved reliability of existing products, developed new products, resolved customer returns for Qualcomm’s design, reliability, packaging and assembly teams to mitigate the risks of failure of products. Process Integration Team Intern, X-FAB Texas Inc., Lubbock, TX September 2005 – April 2006 • Improved reliability of Tungsten Plug vias on 0.25u BiCMOS and CMOS technology automotive products. • Prioritized DoE, SPC, Process integration, troubleshooting process flows, Statistical and data analysis, etc. Executive Engineer, Reliance Communications Inc., Navi Mumbai, INDIA August 2002 – August 2004 • Documented and incorporated changes to finalize standardization documents for Reliance Communications Inc. by collaborating with two consultants from Telcordia Technologies Inc. TECHNICAL SKILLS Analysis Tools: MS Excel 2016 Analytical Problem Solver, XL Data Mining, Tableau. Programming: C, R Programming Circuit design, simulation and layout packages: Cadence design suite, Catena LAYED, PSPICE, Knights database. Failure Analysis Tools & Test Equipment: Hitachi TM-100 Tabletop SEM, B1500A parametric Analyzer, SIRUS Reactive Ion Etcher (RIE), Trion Reactive Ion Etch (RIE), Energy Dispersive X-Ray (EDAX) analyzer, Carbon coater, Agilent Time Domain Reflectometer, UTI Multitrace system 625, Daye XD7600NT X-ray, SONIX Scanning Acoustic Microscope, Tektronix 1180C digital sampling Oscilloscope, JSM -6500F Scanning Electron Microscope, RKD engineering Elite Etch, Digit Concept Sesame 500, Nanomex SEM, Alessi REL-4800 Microprober, Sonix Scanning Acoustic Microscope, Semicaps SPEMS 1350 PEM, QFI Pulse IR, QFI Backside Light Emission Microscopy and XIVA, Phoenix X-Ray system. FA tools used at Texas Instruments Inc.: Karl Suss probe station, Reichert-Jung Polyvar Met, 93K Tester, curve- tracer, Optical microscopes, Hitachi Scanning Electron Microscope (SEM) S-4800, p-lapping T-tool, Decapsulator, pico- probes, B1500A parametric Analyzer, SIRUS Reactive Ion Etcher (RIE), Trion Reactive Ion Etch (RIE), Energy Dispersive X-Ray (EDAX) analyzer, Carbon coater, Agilent Time Domain Reflectometer, UTI Multitrace system 625, Daye XD7600NT X-ray, SONIX Scanning Acoustic Microscope, Tektronix 1180C digital sampling Oscilloscope, Yamato DKN600 constant temperature oven, FEI FIB 800, FEI Dual beam 835, Hamamatsu Photon Emission Microscope, S-4700 Scanning Electron Microscope, Fiber-Lite M1-150 High intensity illuminator, Leica Microscope, Navitar 150 Illuminator, Sirus RFX600A Reactive Ion Etch, Nisene Jet-Etcher, Buehler Ecomet 3 grinder-Polisher, Allied Multiprep polisher, chemical and mechanical tools for failure analysis, Alessi REL-4800 Microprober, Sonix Scanning Acoustic Microscope. Calibration and measurement tools and software: Keithley 2400 & 4200 semiconductor parameter analyzer, HP4284A precision LCR meter, HP 4156B Precision Semiconductor parameter analyzer, Multiscan II and Multiscan III software. PUBLICATIONS • Mass Capitalism: A Blueprint for Economic Revival (2014), Book Publishers Network. • Sustaining Moore's Law: Uncertainty leading to a certainty of IoT Revolution (2015), Morgan & Claypool. • How the Information Revolution remade Business, and the Economy: A Roadmap for Progress of the Semiconductor Industry (2016), Business Expert Press. • Improving Reliability of Tungsten Plug Via on an Integrated Circuitry: Process Flow in BiCMOS and CMOS Technology with Failure Analysis, Design of Experiments, Statistical Analysis and Wafer Maps (2016). ACHIEVEMENTS, HONORS, AWARDS AND ORGANIZATIONS • International Symposium for Testing and Failure Analysis (ISTFA) 2009, 2010 & 2016 – Session Chair • Indian Financial Market Convention 2015, Mumbai – Foreign Exchange Segment Panelist February 2015 ADDITIONAL INFORMATION Eligibility: A U.S. Permanent Resident with no restrictions to work. (Received USPR as extraordinary individual) Languages: Fluent in English, Hindi, Marathi, basic conversation in Mandarin (passed certification exams).