Cadence's Allegro TimingVision environment enables up to 67% faster timing closure of high-speed PCB interfaces.

1. New Allegro TimingVision Environment:
Up to 67% Faster Timing Closure
March 2014

2. Motivation: timing closure on advanced high-speed interfaces
is iterative, frustrating, and time-consuming
VTT
• Market demands products that are
faster, have more bandwidth, and
use less power
Differential Clock
Data Bytelane (5)
Differential Clock
• Increasing use of standards-based
interfaces
– DDR2  DDR3  DDR4
– PCI Express Gen1  Gen2  Gen3
– Supply voltage: 1.8V  1.5V  1.2V
VTT
D
I
M
Data Bytelane (5)
M
D
I
M
M
Address / Command / Control
MEM
CTRLR
V
T
T
Address / Command / Control
Differential Clock
V
T
T
VTT
Data Bytelane (4)
• Increasingly sensitive signals
– Ripples through power supply
– Crosstalk
Complex set of electrical and layout
implementation constraints
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Differential Clock
VTT
Data Bytelane (4)

3. Current: timing closure challenges
DRC mode
 Requires PCB designers to go back and forth between design canvas and Allegro®
Constraint Manager
 Timing closure is an iterative process—fix one byte lane, then fix another, then back to the
first one
 Feedback provided on a matched group level
−
All signals have to meet timing for the group to go green
 All interdependencies and margins between groups are calculated by the PCB designer
manually
3
© 2013 Cadence Design Systems, Inc. All rights reserved.
Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.

4. How Allegro TimingVision environment accelerates
timing closure
Green is good
Red is short
Yellow is long
Stripes indicate the target net
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© 2013 Cadence Design Systems, Inc. All rights reserved.
Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.
1. Embedded timing engine
‒ Analyzes signal
interdependencies to
develop SMART delay
and phase targets
‒ Helps designers develop
strategy to address timing
issues
2. Real-time visual feedback on
design canvas
– Shows color-coded timing
and phase information
– Provides custom data tips
– Allows users to see
beyond physical routing
3. Auto-interactive technologies
‒ Significantly reduce
manual work with Autointeractive Delay Tuning
(AiDT) and Autointeractive Phase Tuning
(AiPT)

5. Allegro TimingVision guiding AiDT
Select complete
interface for
Allegro TimingVision
environment
Select a
byte lane
to tune
AiDT adds
tuning
All nets in the byte
lane are tuned!
5
© 2013 Cadence Design Systems, Inc. All rights reserved.
Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.

6. Allegro TimingVision guiding AiPT
• Meet differential-pair
phase requirements
easily
Out of phase
Phase adjustment
• Static and dynamic
phase compensation
• User-driven controlled
compensation
techniques
Phase bumps
added
6
© 2013 Cadence Design Systems, Inc. All rights reserved.
Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.

7. Assure compliance with memory I/F specifications
• Allegro TimingVision environment
with Cadence Sigrity® poweraware SI analysis can rapidly
implement and assure compliance
with memory interface
specifications
– Modeling SSN necessary for
accurate timing analysis
• Unmatched integrated signal and
power integrity simulation
solutions
– Power-aware signal integrity ensures
accuracy and QoR
– Multi-gigabit serial link solution
predicts BER
– Full power integrity suite enables PI
signoff
– Package and model extraction for
system-level analysis
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© 2013 Cadence Design Systems, Inc. All rights reserved.
Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.

8. Summary – Allegro TimingVision environment
• Innovative, unique environment within the Allegro PCB
Designer solution accelerates timing closure by up to 67%
• Assures compliance with interface specifications in
conjunction with Sigrity® power-aware SI analysis
• Cadence: Only EDA vendor to enable product creation
from IP into SoC package PCB, with system
predictably and cost effectiveness
• Learn more at:
http://www.cadence.com/cadence/Allegro/autointeractive/P
ages/default.aspx
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© 2013 Cadence Design Systems, Inc. All rights reserved.
Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.

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© 2012 Cadence Design Systems, Inc. All rights reserved.