The goal of this project is to specify the functional requirements for the design of discrete Hilbert transform.

1. Design of discrete Hilbert
transform
➢ Realized by: Marwa Bhouri
Rania Ferchichi
➢ ING3: Group n°4
2017/2018

2. 2
Table des matières
Chapter 1: Specification ......................................................................................................................................... 5
I. Introduction .................................................................................................................................................... 6
II. Hilbert transformation ................................................................................................................................... 6
II.1 Description of Hilbert transform using FFT................................................................................................ 6
II.2 APPLICATIONS OF HILBERT TRANSFORM .................................................................................................. 8
II. 3. Hardware architecture of Hilbert transform ........................................................................................... 8
II.3.1 Fast Fourier Transform....................................................................................................................... 9
II.3.2 Inverse fast Fourier transform.......................................................................................................... 12
II.3.3 Controller FSM ................................................................................................................................. 14
Chapter 2: RTL SIMULATION OF Hilbert transform ............................................................................................... 15
I. SIMULATION WAVEFORMS AND RESULT ANALYSIS .................................................................................. 16
Conclusion............................................................................................................................................................ 20
Annex ................................................................................................................................................................. 21

3. 3
List of figures
Figure 1:Architecture of Hilbert Transform............................................................................................................. 8
Figure 2:Illustration of FFT stages for an 8-pt FFT ................................................................................................... 9
Figure 3:DFT Terminology..................................................................................................................................... 11
Figure 4:Architecture of FFT ................................................................................................................................. 12
Figure 5:IFFT for N=8 ............................................................................................................................................ 13
Figure 6:Finite state machine ............................................................................................................................... 14
Figure 7:Simulation under Matlab........................................................................................................................ 17
Figure 8:Results given by Matlab.......................................................................................................................... 18
Figure 9:Results given by Cadence........................................................................................................................ 18
Figure 10:Results of code coverage ...................................................................................................................... 19
Table 1:Comparison of results given by Cadence and Matlab.............................................................................. 16

4. 4
Introduction
Over the years of its development, the integrated circuit technology has brought great
progress to the design of high performance systems.
VHDL is an acronym for VHSIC Hardware Description language (VHSIC stands for Very High
Speed Integrated Circuits). It is a hardware description language that can be used to model a
digital system at many levels of abstraction ranging from the algorithmic level to the gate
level. The complexity of the digital system being modeled could vary from that of a simple
gate to a complete digital electronic system, or anything in between. VHDL can be regarded as
an integrated amalgamation of the following languages (sequential + concurrent + netlist +
timing +specification + waveform generation language). Therefore, the language has
constructs that enable to express the concurrent or sequential behavior of a digital system
with or without timing. It also allows modeling the system as an interconnection of
components. Test waveforms can also be generated using the same constructs. All the above
constructs can be combined to provide a comprehensive description of the system in a single
model.
In this report, we present the design stages of the Hilbert transform.

5. 5
Chapter 1: Specification

6. 6
I. Introduction
The goal of this chapter is to specify the functional requirements for the design and define the
external interfaces to the related designs.
II. Hilbert transformation
II.1 Description of Hilbert transform using FFT
The Hilbert transformation, similarly used as Hilbert transformer which deals with signals in
time domain, was first introduced to signal theory by Denis Gabor in 1998.
Discrete HT is a very important technique in signal and network theory and it also has very
practical applications in various fields. The fields may also include communication systems,
RADAR systems and medical imaging.
A Hilbert transform is a convolutional operator which is commonly referred to as a wide band
90° phase shifter.
𝐱(𝐧) 𝐚 = 𝐱(𝐧) + 𝐢 ∗ 𝐱̂(𝐧) (𝟏)
Every analytic signal has a real part x(n), which is the original data, and an imaginary
part, 𝐱̂(𝐧), which contains the Hilbert transform. The imaginary part is a version of the
original real sequence with a 90° phase shift.
The most widely used method for computing the discrete HT is through the use of the FFT.
It is defined as:
𝐱̂(𝐧) = 𝐱(𝐧) ∗ 𝐡(𝐧) (𝟐)
Where h(n) is the impulse of discrete HT given by
𝐡(𝐧) =
{
𝟏, 𝐧 = 𝟎,
𝐍
𝟐
(𝟑)
𝟐, 𝟏 ≤ 𝐧 ≤
𝐍
𝟐
− 𝟏
𝟎,
𝐍
𝟐
+ 𝟏 ≤ 𝐧 ≤ 𝐍 − 𝟏

7. 7
The discrete HT can be computed via FFT as shown below, where X(m) is the Fourier
transform of input signal x(n)
𝐱̂(𝐧) = 𝐈𝐅𝐅𝐓(𝐗(𝐦)𝐡(𝐦) ) (𝟒)
It is evident that the DHT can be calculated easily by FFT in three steps. This method
transforms the input sequence to the frequency domain, then computes the Hilbert transform
in the frequency domain and finally performs an IFFT operation to get the required Hilbert-
transformed sequence.
A large number of FFT algorithms have been developed such as radix-2 algorithms, Winograd
algorithm (WFTA), prime factor algorithms (FPA), and fast Hartley transform (FHT). These
methods use different transforms to compute the discrete HT, their basic method of
computing the discrete HT is that they all use the transform domain for computing it. There
are other methods, such as the filter method and the systolic arrays.
This method comes directly from the discrete HT definition. This method is the direct
implementation of the convolution operation on the input sequence with the impulse
response of the Hilbert transformer. The filter method requires considerable memory in cases
of higher accurate requirement. The systolic arrays method computes the constant parameter
matrix beforehand, and then multiplies the input data by this matrix, but the processing unit
of the systolic arrays is difficult to implement. For hardware implementation, architectures of
discrete HT processor based on FFT algorithms can be generally grouped into pipelined and
memory based architecture styles.

8. 8
II.2 APPLICATIONS OF HILBERT TRANSFORM
This transform is therefore useful for diverse purposes such as latency analysis in neuro-
physiological signals, design of bizarre stimuli for psychoacoustic experiments, speech data
compression for communication, regularization of convergence problems in multi-channel
acoustic echo cancellation, and signal processing for auditory prostheses.
In telecommunication, Hilbert transform (HT) is an analytical tool that is useful for the
representation of certain kinds of signals such as band pass signals. This transform is also used
for various kinds of modulation schemes as series side band AM modulation.
In electrocardiography, The Hilbert transform is a widely used tool in interpreting
electrocardiograms (ECGs). It facilitates the detection of the QRS complex in a ECG signal.
II. 3. Hardware architecture of Hilbert transform
The proposed hardware architecture is shown in Figure 1.
The architecture consists of three basic blocks:
- FFT, multiplication with the impulse of discrete HT.
-IFFT.
-FSM to control all system.
Figure 1:Architecture of Hilbert Transform

9. 9
II.3.1 Fast Fourier Transform
In digital signal processing, many algorithms such as convolution, filtering, and spectral
analysis can be implemented by fast Fourier transform (FFT). The FFT has become the most
basic algorithms of DSP, and is widely used in power equipment monitoring and fault
diagnosis system. There is a constant need for faster and better FFT algorithms. Namely, the
FFT algorithm relies on a divide-and-conquer methodology, which divides the N coefficient
points into smaller blocks in different stages. This iterative nature of the algorithm with
individual computation of smaller blocks is ideal for a FSM design. The FSM in the design
controls the main loop of the system, as we go from one stage to the next, while a FSM
controls the computation of the coefficients within each block.
We compute the first stage with groups of two coefficients, yielding N/2 blocks, each
computing the addition and subtraction of the coefficients scaled by the corresponding
twiddle factors (called a “butterfly” for its cross-over appearance). These results are used to
compute the next state of N/4 blocks, which will then combine the results of two previous
blocks (combining 4 coefficients at this point). This process repeats until we have one main
block, with a final computation of all N coefficients. We choose to work with N=8 as
mentioned below.
Figure 2:Illustration of FFT stages for an 8-pt FFT
➢ Radix 2 Decimation-in-Time
The main idea behind DIT algorithm is to divide an N-length sequence in the time domain into
two
𝑵
𝟐
length sequences by separating even and odd samples of x(n).
Then separating
𝑵
𝟐
length sequences into two
𝑵
𝟒
length sequences and so on. This division of
sequence continues until 2-point sequences. Then apply DFT on 2-point sequences.
To find the DFT a of N-point sequence, an additional coefficient matrix needed. The radix 2
decimation-in-time algorithm can only be used if the sequence length N is integer power of 2.

10. 10
The FFT computation process for N-point sequence x(n) is explained mathematically in the
following sentences.
x(n) is N-length sequence and is divided into two
𝑵
𝟐
sequences as
Where :
If we assume 𝐰 𝐍
𝐧
= 𝐞
−𝐣𝟐𝛑𝐧
𝐍 then we can write X(k) as
Where X1(k), X2(k) are DFTs of x1(n) and x2(n) and 𝐰 𝐍
𝐤
is coefficient vector.
The DFT X(k) of N-point sequence is calculated by multiplying X2(k) with 𝐰 𝐍
𝐤
and then adding
the result to X1(k).
so, we can conclude that FFT is defined as:
𝐗(𝐦) = ∑ 𝐱(𝐧) ∗𝐍−𝟏
𝐧=𝟎 𝐰 𝐍
𝐧
The twiddle factor 𝐰 𝐍
𝐧
= 𝐞
−𝐣𝟐𝛑𝐧
𝐍
For one butterfly
𝐀′
= 𝐀 + 𝐰 𝐍
𝐧
∗ 𝐁
𝐁′
= 𝐀 − 𝐰 𝐍
𝐧
∗ 𝐁
As shown in Figure 2, the discrete Fourier transform changes an N point input signal into two
point output signals. The input signal contains the amplitude of the signal being decomposed,
while the two output signals contain the amplitudes of the component sine and cosine waves
(scaled in a way we will discuss shortly). The input signal is said to be in the time domain. This
is because the most common type of signal entering the DFT is composed of samples which
are obtained at regular intervals of time.
fft makes it possible to go from the time domain to the frequency domain (figure)

11. 11
Figure 3:DFT Terminology
➢ Architecture of FFT
• Structure Model of Floating-point FFT
Operation of the processor consists of three parts: data input, FFT computation and data
output. As shown in figure 4, FFT processor includes four radix-2 butterfly, a coefficient ROM,
a controller, 8 multiplexer.

12. 12
Figure 4:Architecture of FFT
II.3.2 Inverse fast Fourier transform
We compute the first stage with groups of four coefficients, yielding N/2 blocks, each
computing the addition and subtraction of the coefficients scaled by the corresponding
twiddle factors (called a “butterfly” for its cross-over appearance). These results are used to
compute the next state of N/4 blocks, which will then combine the results of two previous
blocks (combining 4 coefficients at this point). This process repeats until we have one main
block, with a final computation of all N coefficients. We choose to work with N=8 as
mentioned below
BF0
BF1
BF2
BF3
ROM
enenselsel
enen
selsel
enen
enen
selsel
selsel
Inputs
clkclk
rstrst
readread
addadd
clkclk rstrst calcal
clkclk rstrst calcal
clkclk rstrst calcal
clkclk rstrst calcal
outputs
outout

13. 13
Figure 5:IFFT for N=8
The IFFT is defined as:
𝐱(𝐧) =
𝟏
𝐍
∑ 𝐱(𝐦) ∗ 𝐰 𝐍
−𝐦
𝐍−𝟏
𝐦=𝟎
The twiddle factor 𝐰 𝐍
𝐦
= 𝐞
−𝐣𝟐𝛑𝐦
𝐍
𝐀𝐫′
= 𝐑𝐞(𝐀) + 𝐑𝐞(𝐁)
𝐀𝐢′
= 𝐈𝐦(𝐀) + 𝐈𝐦(𝐁)
𝐁𝐫′
= 𝐰 𝐍𝐫
𝐧
∗ (𝐑𝐞(𝐀) − 𝐑𝐞(𝐁)) + 𝐰 𝐍𝐢
𝐧
∗ (𝐈𝐦(𝐁) − 𝐈𝐦(𝐀))
𝐁𝐢′
= 𝐰 𝐍𝐫
𝐧
∗ (𝐈𝐦(𝐀) − 𝐈𝐦(𝐁)) + 𝐰 𝐍𝐢
𝐧
∗ (𝐑𝐞(𝐀) − 𝐑𝐞(𝐁))

14. 14
II.3.3 Controller FSM
The controller is modeled as a finite state machine. It has 20 states.
Figure 6:Finite state machine

15. 15
Chapter 2: RTL SIMULATION OF Hilbert
transform

16. 16
I. SIMULATION WAVEFORMS AND RESULT ANALYSIS
The implementation of the design in VHDL is verified by simulating the design. A test bench is
written for the purpose. It reads the input data. It also instantiates the various components
and provides the main entity with the signals such as clock and reset. The results of simulation
and a comparison with the results of Matlab are given below.
for an input vector equal to x = [0,2,3, -1,0,12,0,4]
we obtain the following results.
The theoretical value of Matlab Cadence simulation results
Y0 0+2.5533i 0+2.0606258i
Y1 2- 1.8107i 2-1.81065i
Y2 3+0.9822i 3+0.9822501i
Y3 -1+1.8107i -1+1.8106499i
Y4 0- 8.0533i 0-8.053249i
Y5 12+0.3107i 12+0.31065i
Y6 0+ 4.5178i 0+4.51775i
Y7 4- 0.3107i 4-0.31064987
Tableau 1:Comparison of results given by Cadence and Matlab
The table 1 shows that cadence simulation results are well consistent with theoretical values
of Matlab.
 the results under MATLAB and under cadence are almost equal.

17. 17
➢ Matlab code
➢ Simulation under Matlab
Figure 7:Simulation under Matlab
1 2 3 4 5 6 7 8
-5
0
5
10
15
partie reel de y
1 2 3 4 5 6 7 8
-10
-5
0
5
transformee de Hilbert de x

18. 18
Figure 8:Results given by Matlab
Besides, we selected many sets of data to simulate in cadence:
x1 = [0,2,3,-1,0,12,0,4]
x2 = [7,-5,2,-1,0,-11,2,4]
x3= [14,-4,0,0,-11,2,2,2]
x4 = [14,-4.5,0,1.3,-1,-1,7,8]
x5 = [14,0,9,8,-5,0,0,0]
x6 = [3.5,-2,-1.3,4,6,-6,8,4.5]
Figure 9:Results given by Cadence

19. 19
➢ ANALYSIS OF CODE COVERAGE
The major problem of the simulation approach is to choose a good metric to gauge the quality
of the test pattern. One popular metric of verifying the design written in HDL is the code
coverage metric in software testing.
Figure8 show coverage of sub-modules in the Hilbert Transform(HT) processor and that of the
test platform after two test vectors run. The results are very encouraging: the coverage of
expression was 100%, the coverage of HT processor control module was as high as 100%.
Figure 10:Results of code coverage

20. 20
Conclusion
We are thankful to our project instructor, Mr.Maaref Ibrahim for giving us this wonderful
opportunity to do a project under his guidance. The love and faith that he showered on us
have helped us to go on and complete this project.

21. 21
Annex
Code vhdl of Hilbert transform
---------Datapath_top
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.float_pkg.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity Datapath_top is
Port ( xh0_r,xh1_r,xh2_r,xh3_r,xh4_r,xh5_r,xh6_r,xh7_r : in float32;
xh0_i,xh1_i,xh2_i,xh3_i,xh4_i,xh5_i,xh6_i,xh7_i : in float32;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
yh0_r,yh1_r,yh2_r,yh3_r,yh4_r,yh5_r,yh6_r,yh7_r : out float32;
yh0_i,yh1_i,yh2_i,yh3_i,yh4_i,yh5_i,yh6_i,yh7_i : out float32);
end Datapath_top;
architecture Behavioral of Datapath_top is
component datapath1_fft_h is
Port ( x0_r,x1_r,x2_r,x3_r,x4_r,x5_r,x6_r,x7_r : in float32;
x0_i,x1_i,x2_i,x3_i,x4_i,x5_i,x6_i,x7_i : in float32;
clk ,ld_textt,r_romt: in STD_LOGIC;
reset : in STD_LOGIC;
validout:out integer;
out_y,cal,emux:in STD_LOGIC;
ar_rom0,ar_rom1,ar_rom2,ar_rom3,ar_rom4,ar_rom5,ar_rom6,ar_rom7:in integer;
selm1,selm2,selm3,selm4,selm5,selm6,selm7,selm8:in STD_LOGIC_vector(3 downto
0);
y0_r,y1_r,y2_r,y3_r,y4_r,y5_r,y6_r,y7_r : out float32;
y0_i,y1_i,y2_i,y3_i,y4_i,y5_i,y6_i,y7_i : out float32);
end component;
component ifft is
Port ( x0_r,x1_r,x2_r,x3_r,x4_r,x5_r,x6_r,x7_r : in float32;
x0_i,x1_i,x2_i,x3_i,x4_i,x5_i,x6_i,x7_i : in float32;
clk ,ld_textt,r_romt: in STD_LOGIC;
reset: in STD_LOGIC;
validout:out integer;
out_y,cal,emux:in STD_LOGIC;

22. 22
ar_rom0,ar_rom1,ar_rom2,ar_rom3,ar_rom4,ar_rom5,ar_rom6,ar_rom7:in integer;
selm1,selm2,selm3,selm4,selm5,selm6,selm7,selm8:in STD_LOGIC_vector(3 downto
0);
y0_r,y1_r,y2_r,y3_r,y4_r,y5_r,y6_r,y7_r : out float32;
y0_i,y1_i,y2_i,y3_i,y4_i,y5_i,y6_i,y7_i : out float32);
end component;
component fsm is
Port (
clk,reset: in STD_LOGIC;
valid0,valid1:in integer;
ld_textt,r_romt: out STD_LOGIC;
out_y0,out_y00,cal,emux:out STD_LOGIC;
ar_rom0,ar_rom1,ar_rom2,ar_rom3,ar_rom4,ar_rom5,ar_rom6,ar_rom7:out integer;
selm1,selm2,selm3,selm4,selm5,selm6,selm7,selm8:out STD_LOGIC_vector(3 downto
0));
end component;
signal ld_text1,w_ramt1,r_ramt1,r_romt1,out_y1,out_y2,cal1,emux1 :STD_LOGIC;
signal a1r_rom0,a1r_rom1,a1r_rom2,a1r_rom3,a1r_rom4,a1r_rom5,a1r_rom6,a1r_rom7:integer;
signal s1elm1,s1elm2,s1elm3,s1elm4,s1elm5,s1elm6,s1elm7,s1elm8:STD_LOGIC_vector(3 downto 0);
signal yy0_r,yy1_r,yy2_r,yy3_r,yy4_r,yy5_r,yy6_r,yy7_r,yy0_i,yy1_i,yy2_i,yy3_i,yy4_i,yy5_i,yy6_i,yy7_i: float32;
signal yyh0_r,yyh1_r,yyh2_r,yyh3_r,yyh4_r,yyh5_r,yyh6_r,yyh7_r : float32;
signal yyh0_i,yyh1_i,yyh2_i,yyh3_i,yyh4_i,yyh5_i,yyh6_i,yyh7_i : float32;
signal yyy0_r,yyy1_r,yyy2_r,yyy3_r,yyy4_r,yyy5_r,yyy6_r,yyy7_r : float32;
signal yyy0_i,yyy1_i,yyy2_i,yyy3_i,yyy4_i,yyy5_i,yyy6_i,yyy7_i : float32;
signal valid00: integer;
signal valid01: integer;
signal xxh0_r,xxh1_r,xxh2_r,xxh3_r,xxh4_r,xxh5_r,xxh6_r,xxh7_r : float32;
signal xxh0_i,xxh1_i,xxh2_i,xxh3_i,xxh4_i,xxh5_i,xxh6_i,xxh7_i : float32;
begin
p1: fsm port
map(clk,reset,valid00,valid01,ld_text1,r_romt1,out_y1,out_y2,cal1,emux1,a1r_rom0,a1r_rom1,a1r_rom2,a1r_ro
m3,a1r_rom4,a1r_rom5,a1r_rom6,a1r_rom7,s1elm1,s1elm2,s1elm3,s1elm4,s1elm5,s1elm6,s1elm7,s1elm8);
p2: datapath1_fft_h port
map(xh0_r,xh1_r,xh2_r,xh3_r,xh4_r,xh5_r,xh6_r,xh7_r,xh0_i,xh1_i,xh2_i,xh3_i,xh4_i,xh5_i,xh6_i,xh7_i,clk,ld_te
xt1,r_romt1,reset,valid00,out_y1,cal1,emux1,a1r_rom0,a1r_rom1,a1r_rom2,a1r_rom3,a1r_rom4,a1r_rom5,a1r_
rom6,a1r_rom7,s1elm1,s1elm2,s1elm3,s1elm4,s1elm5,s1elm6,s1elm7,s1elm8,yy0_r,yy1_r,yy2_r,yy3_r,yy4_r,yy5
_r,yy6_r,yy7_r,yy0_i,yy1_i,yy2_i,yy3_i,yy4_i,yy5_i,yy6_i,yy7_i);
p3: ifft port
map(yy0_r,yy1_r,yy2_r,yy3_r,yy4_r,yy5_r,yy6_r,yy7_r,yy0_i,yy1_i,yy2_i,yy3_i,yy4_i,yy5_i,yy6_i,yy7_i,clk,ld_text
1,r_romt1,reset,valid01,out_y2,cal1,emux1,a1r_rom0,a1r_rom1,a1r_rom2,a1r_rom3,a1r_rom4,a1r_rom5,a1r_ro
m6,a1r_rom7,s1elm1,s1elm2,s1elm3,s1elm4,s1elm5,s1elm6,s1elm7,s1elm8,yyy0_r,yyy1_r,yyy2_r,yyy3_r,yyy4_r,
yyy5_r,yyy6_r,yyy7_r,yyy0_i,yyy1_i,yyy2_i,yyy3_i,yyy4_i,yyy5_i,yyy6_i,yyy7_i);
process(clk,reset)
begin
if (reset='1') then

23. 23
yh0_r<=x"00000000";
yh0_i<=x"00000000";
yh1_r<=x"00000000";
yh1_i<=x"00000000";
yh2_r<=x"00000000";
yh2_i<=x"00000000";
yh3_r<=x"00000000";
yh3_i<=x"00000000";
yh4_r<=x"00000000";
yh4_i<=x"00000000";
yh5_r<=x"00000000";
yh5_i<=x"00000000";
yh6_r<=x"00000000";
yh6_i<=x"00000000";
yh7_r<=x"00000000";
yh7_i<=x"00000000";
elsif (clk 'event and clk='1') then
if(out_y2='1') then
yh0_r<=yyy0_r;
yh0_i<=yyy0_i;
yh1_r<=yyy1_r;
yh1_i<=yyy1_i;
yh2_r<=yyy2_r;
yh2_i<=yyy2_i;
yh3_r<=yyy3_r;
yh3_i<=yyy3_i;
yh4_r<=yyy4_r;
yh4_i<=yyy4_i;
yh5_r<=yyy5_r;
yh5_i<=yyy5_i;
yh6_r<=yyy6_r;
yh6_i<=yyy6_i;
yh7_r<=yyy7_r;
yh7_i<=yyy7_i;
end if;
end if;
end process;
end Behavioral;

24. 24
------Hilbret_transform_tb
-- TestBench Template
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.float_pkg.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
ENTITY Hilbret_transform_tb IS
END Hilbret_transform_tb;
ARCHITECTURE behavior OF Hilbret_transform_tb IS
-- Component Declaration
COMPONENT Datapath_top
Port ( xh0_r,xh1_r,xh2_r,xh3_r,xh4_r,xh5_r,xh6_r,xh7_r : in float32;
xh0_i,xh1_i,xh2_i,xh3_i,xh4_i,xh5_i,xh6_i,xh7_i : in float32;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
yh0_r,yh1_r,yh2_r,yh3_r,yh4_r,yh5_r,yh6_r,yh7_r : out float32;
yh0_i,yh1_i,yh2_i,yh3_i,yh4_i,yh5_i,yh6_i,yh7_i : out float32);
END COMPONENT;
SIGNAL xh0_r,xh1_r,xh2_r,xh3_r,xh4_r,xh5_r,xh6_r,xh7_r : float32;
SIGNAL xh0_i,xh1_i,xh2_i,xh3_i,xh4_i,xh5_i,xh6_i,xh7_i : float32;
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal yh0_r,yh1_r,yh2_r,yh3_r,yh4_r,yh5_r,yh6_r,yh7_r : float32;
signal yh0_i,yh1_i,yh2_i,yh3_i,yh4_i,yh5_i,yh6_i,yh7_i : float32;
BEGIN
-- Component Instantiation
uut: Datapath_top PORT MAP(xh0_r=>xh0_r
,xh1_r=>xh1_r,xh2_r=>xh2_r,xh3_r=>xh3_r,xh4_r=>xh4_r,xh5_r=>xh5_r,xh6_r=>xh6_r,xh7_r=>xh7_r,
xh0_i=>xh0_i,xh1_i=>xh1_i,xh2_i=>xh2_i,xh3_i=>xh3_i,xh4_i=>xh4_i,xh5_i=>xh5_i,xh6_i=>xh6_i,xh7_i=>xh7_i,
clk=>clk,reset=>reset,
yh0_r=>yh0_r,yh1_r=>yh1_r,yh2_r=>yh2_r,yh3_r=>yh3_r,yh4_r=>yh4_r,yh5_r=>yh5_r,yh6_r=>yh6_r,yh7_r=>yh7
_r,
yh0_i=>yh0_i,yh1_i=>yh1_i,yh2_i=>yh2_i,yh3_i=>yh3_i,yh4_i=>yh4_i,yh5_i=>yh5_i,yh6_i=>yh6_i,yh7_i=>yh7_i);

25. 25
clk_process :process
begin
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
end process;
reset<='1','0' after 6 ns;
--reset<='1','0' after 6 ns,'1' after 400 ns,'0' after 500 ns;
tb1 : PROCESS
BEGIN
-------x1
xh0_r <= x"00000000";--0
xh1_r <= x"40000000";--2
xh2_r <= x"40400000";--3
xh3_r <= x"bf800000";--(-1)
xh4_r <= x"00000000";--0
xh5_r <= x"41400000";--12
xh6_r <= x"00000000";--0
xh7_r <= x"40800000";--4
xh0_i <= x"00000000";--0
xh1_i <= x"00000000";
xh2_i <= x"00000000";
xh3_i <= x"00000000";
xh4_i <= x"00000000";
xh5_i <= x"00000000";
xh6_i <= x"00000000";
xh7_i <= x"00000000";
wait for 230 ns;
-----x2
xh0_r <= x"40e00000";--7
xh1_r <= x"c0a00000";--(-5)
xh2_r <= x"40000000";--2
xh3_r <= x"bf800000";--(-1)
xh4_r <= x"00000000";--0
xh5_r <= x"c1300000";--(-11)
xh6_r <= x"40000000";--2
xh7_r <= x"40800000";--4
xh0_i <= x"00000000";
xh1_i <= x"00000000";
xh2_i <= x"00000000";
xh3_i <= x"00000000";
xh4_i <= x"00000000";
xh5_i <= x"00000000";
xh6_i <= x"00000000";
xh7_i <= x"00000000";
wait for 230 ns;
----------x3
xh0_r <= x"41600000";--14

26. 26
xh1_r <= x"c0800000";--(-4)
xh2_r <= x"00000000";--0
xh3_r <= x"00000000";--0
xh4_r <= x"c1300000";--(-11)
xh5_r <= x"40000000";--2
xh6_r <= x"40000000";--2
xh7_r <= x"40000000";--2
xh0_i <= x"00000000";
xh1_i <= x"00000000";
xh2_i <= x"00000000";
xh3_i <= x"00000000";
xh4_i <= x"00000000";
xh5_i <= x"00000000";
xh6_i <= x"00000000";
xh7_i <= x"00000000";
wait for 230 ns;
------------x4
xh0_r <= x"41600000";--14
xh1_r <= x"c0900000";--(-4.5)
xh2_r <= x"00000000";--0
xh3_r <= x"3fa66666";--1.3
xh4_r <= x"bf800000";--(-1 )
xh5_r <= x"bf800000";--(-1 )
xh6_r <= x"40e00000";--7
xh7_r <= x"41000000";--8
xh0_i <= x"00000000";
xh1_i <= x"00000000";
xh2_i <= x"00000000";
xh3_i <= x"00000000";
xh4_i <= x"00000000";
xh5_i <= x"00000000";
xh6_i <= x"00000000";
xh7_i <= x"00000000";
wait for 230 ns;
-------------------x5
xh0_r <= x"41600000";--14
xh1_r <= x"00000000";--0
xh2_r <= x"41100000";--9
xh3_r <= x"41000000";--8
xh4_r <= x"c0a00000";--(-5)
xh5_r <= x"00000000";--0
xh6_r <= x"00000000";--0
xh7_r <= x"00000000";--0
xh0_i <= x"00000000";
xh1_i <= x"00000000";
xh2_i <= x"00000000";
xh3_i <= x"00000000";
xh4_i <= x"00000000";
xh5_i <= x"00000000";
xh6_i <= x"00000000";
xh7_i <= x"00000000";
wait for 230 ns;

27. 27
-------------x6
xh0_r <= x"40600000";--3.5
xh1_r <= x"c0000000";--(-2)
xh2_r <= x"bfa66666";--(-1.3)
xh3_r <= x"40800000";--4
xh4_r <= x"40c00000";--6
xh5_r <= x"c0c00000";--(-6 )
xh6_r <= x"41000000";--8
xh7_r <= x"40900000";--4.5
xh0_i <= x"00000000";
xh1_i <= x"00000000";
xh2_i <= x"00000000";
xh3_i <= x"00000000";
xh4_i <= x"00000000";
xh5_i <= x"00000000";
xh6_i <= x"00000000";
xh7_i <= x"00000000";
wait for 230 ns;
END PROCESS tb1;
END;