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Organisasi dan Arsitektur
Komputer
Ajeng Savitri Puspaningrum, M.Kom
Pertemuan 27
Memory (Part 3)
 Learning Kind of Memory
Semiconductor Memory
 RAM
 Misnamed as all semiconductor memory is random access
 Read/Write
 Volatile
 Temporary storage
 Static or dynamic
RAM
(Random Acess Memory)
Perangkat random-access memungkinkan disimpan data
yang dapat diakses secara langsung dalam urutan acak.
Main Memory
Jenis RAM
Dynamic RAM (DRAM)
Synchronous
DRAM (SDRAM)
Rambus DRAM (RDRAM)
Extended Data Output RAM
(EDORAM)
Static Random Acess Memory
Double Data Rate SDRAM (DDR SDRAM)
Main Memory
Dynamic RAM
 Bits stored as charge in capacitors
 Charges leak
 Need refreshing even when powered
 Simpler construction
 Smaller per bit
 Less expensive
 Need refresh circuits
 Slower
 Main memory
 Essentially analogue
 Level of charge determines value
DRAM Operation
 Address line active when bit read or written
 Transistor switch closed (current flows)
 Write
 Voltage to bit line
 High for 1 low for 0
 Then signal address line
 Transfers charge to capacitor
 Read
 Address line selected
 transistor turns on
 Charge from capacitor fed via bit line to sense amplifier
 Compares with reference value to determine 0 or 1
 Capacitor charge must be restored
Static RAM
 Bits stored as on/off switches
 No charges to leak
 No refreshing needed when powered
 More complex construction
 Larger per bit
 More expensive
 Does not need refresh circuits
 Faster
 Cache
 Digital
 Uses flip-flops
Static RAM Operation
 Transistor arrangement gives stable logic state
 State 1
 C1 high, C2 low
 T1 T4 off, T2 T3 on
 State 0
 C2 high, C1 low
 T2 T3 off, T1 T4 on
 Address line transistors T5 T6 is switch
 Write – apply value to B & compliment to B
 Read – value is on line B
SRAM v DRAM
 Both volatile
 Power needed to preserve data
 Dynamic cell
 Simpler to build, smaller
 More dense
 Less expensive
 Needs refresh
 Larger memory units
 Static
 Faster
 Cache
Advanced DRAM Organization
 Basic DRAM same since first RAM chips
 Enhanced DRAM
 Contains small SRAM as well
 SRAM holds last line read (c.f. Cache!)
 Cache DRAM
 Larger SRAM component
 Use as cache or serial buffer
Synchronous DRAM (SDRAM)
 Access is synchronized with an external clock
 Address is presented to RAM
 RAM finds data (CPU waits in conventional DRAM)
 Since SDRAM moves data in time with system clock, CPU
knows when data will be ready
 CPU does not have to wait, it can do something else
 Burst mode allows SDRAM to set up stream of data and fire
it out in block
 DDR-SDRAM sends data twice per clock cycle (leading &
trailing edge)
RAMBUS
 Adopted by Intel for Pentium & Itanium
 Main competitor to SDRAM
 Vertical package – all pins on one side
 Data exchange over 28 wires < cm long
 Bus addresses up to 320 RDRAM chips at 1.6Gbps
 Asynchronous block protocol
 480ns access time
 Then 1.6 Gbps
DDR SDRAM
 SDRAM can only send data once per clock
 Double-data-rate SDRAM can send data twice per clock
cycle
 Rising edge and falling edge
Cache DRAM
 Mitsubishi
 Integrates small SRAM cache (16 kb) onto generic DRAM
chip
 Used as true cache
 64-bit lines
 Effective for ordinary random access
 To support serial access of block of data
 E.g. refresh bit-mapped screen
CDRAM can prefetch data from DRAM into SRAM buffer
Subsequent accesses solely to SRAM
Read Only Memory (ROM)
 Permanent storage
 Nonvolatile
 Microprogramming (see later)
 Library subroutines
 Systems programs (BIOS)
 Function tables
ROM
(Read Only Memory)
ROM ini sifatnya permanen, artinya program / data yang disimpan di dalam
ROM ini tidak mudah hilang atau berubah walau aliran listrik di matikan.
Salah satu contoh ROM adalah ROM BIOS yang berisi program dasar
system komputer yang mengatur / menyiapkan semua peralatan /
komponen yang ada dalam komputer saat komputer dihidupkan.
Main Memory
Types of ROM
 Written during manufacture
 Very expensive for small runs
 Programmable (once)
 PROM
 Needs special equipment to program
 Read “mostly”
 Erasable Programmable (EPROM)
 Erased by UV
 Electrically Erasable (EEPROM)
 Takes much longer to write than read
 Flash memory
 Erase whole memory electrically
Organisation In Detail
 A 16Mbit chip can be organised as 1M of 16 bit words
 A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in
chip 1 and so on
 A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array
 Reduces number of address pins
 Multiplex row address and column address
 11 pins to address (211=2048)
 Adding one more pin doubles range of values so x4 capacity
Refreshing
 Refresh circuit included on chip
 Disable chip
 Count through rows
 Read & Write back
 Takes time
 Slows down apparent performance
Interleaved Memory
 Collection of DRAM chips
 Grouped into memory bank
 Banks independently service read or write requests
 K banks can service k requests simultaneously
Error Correction
 Hard Failure
 Permanent defect
 Soft Error
 Random, non-destructive
 No permanent damage to memory
 Detected using Hamming error correcting code
Jenis ROM
Mask ROM
Programmable Read Only Memory
(Eraseable Programmable Read Only Memory)
EPROM
Electrically Erasable Programmable Read Only Memory
Main Memory
CMOS
(Complementary Metal Oxide Semiconductor)
Suatu memori yang khusus yang berisi data
vital mengenai konfigurasi komputer dan
bersifat semi-permanen.
Main Memory
Virtual Memory
Teknik manajemen memori yang dikembangkan untuk kernel
multitugas.
Memungkinkan sebuah program harus dirancang seolah-olah
hanya ada satu jenis memori, memori "virtual", yang bertindak
secara langsung beralamat memori baca/tulis (RAM).
Main Memory
Refference
Stalling, William, Computer Organization
and Architecture, 10th Edition, Pearson,
2015
Abdurohman, Maman, Organisasi dan
Arsitektur Komputer revisi ke-4, Penerbit
Informatika, 2017
Terima Kasih
ajeng.savitri@teknokrat.ac.id
https://teknokrat.ac.id/en/
https://spada.teknokrat.ac.id/

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Memory (Part 3)

  • 1. Organisasi dan Arsitektur Komputer Ajeng Savitri Puspaningrum, M.Kom Pertemuan 27
  • 3.  Learning Kind of Memory
  • 4. Semiconductor Memory  RAM  Misnamed as all semiconductor memory is random access  Read/Write  Volatile  Temporary storage  Static or dynamic
  • 5. RAM (Random Acess Memory) Perangkat random-access memungkinkan disimpan data yang dapat diakses secara langsung dalam urutan acak. Main Memory
  • 6. Jenis RAM Dynamic RAM (DRAM) Synchronous DRAM (SDRAM) Rambus DRAM (RDRAM) Extended Data Output RAM (EDORAM) Static Random Acess Memory Double Data Rate SDRAM (DDR SDRAM) Main Memory
  • 7. Dynamic RAM  Bits stored as charge in capacitors  Charges leak  Need refreshing even when powered  Simpler construction  Smaller per bit  Less expensive  Need refresh circuits  Slower  Main memory  Essentially analogue  Level of charge determines value
  • 8. DRAM Operation  Address line active when bit read or written  Transistor switch closed (current flows)  Write  Voltage to bit line  High for 1 low for 0  Then signal address line  Transfers charge to capacitor  Read  Address line selected  transistor turns on  Charge from capacitor fed via bit line to sense amplifier  Compares with reference value to determine 0 or 1  Capacitor charge must be restored
  • 9. Static RAM  Bits stored as on/off switches  No charges to leak  No refreshing needed when powered  More complex construction  Larger per bit  More expensive  Does not need refresh circuits  Faster  Cache  Digital  Uses flip-flops
  • 10. Static RAM Operation  Transistor arrangement gives stable logic state  State 1  C1 high, C2 low  T1 T4 off, T2 T3 on  State 0  C2 high, C1 low  T2 T3 off, T1 T4 on  Address line transistors T5 T6 is switch  Write – apply value to B & compliment to B  Read – value is on line B
  • 11. SRAM v DRAM  Both volatile  Power needed to preserve data  Dynamic cell  Simpler to build, smaller  More dense  Less expensive  Needs refresh  Larger memory units  Static  Faster  Cache
  • 12. Advanced DRAM Organization  Basic DRAM same since first RAM chips  Enhanced DRAM  Contains small SRAM as well  SRAM holds last line read (c.f. Cache!)  Cache DRAM  Larger SRAM component  Use as cache or serial buffer
  • 13. Synchronous DRAM (SDRAM)  Access is synchronized with an external clock  Address is presented to RAM  RAM finds data (CPU waits in conventional DRAM)  Since SDRAM moves data in time with system clock, CPU knows when data will be ready  CPU does not have to wait, it can do something else  Burst mode allows SDRAM to set up stream of data and fire it out in block  DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)
  • 14. RAMBUS  Adopted by Intel for Pentium & Itanium  Main competitor to SDRAM  Vertical package – all pins on one side  Data exchange over 28 wires < cm long  Bus addresses up to 320 RDRAM chips at 1.6Gbps  Asynchronous block protocol  480ns access time  Then 1.6 Gbps
  • 15. DDR SDRAM  SDRAM can only send data once per clock  Double-data-rate SDRAM can send data twice per clock cycle  Rising edge and falling edge
  • 16. Cache DRAM  Mitsubishi  Integrates small SRAM cache (16 kb) onto generic DRAM chip  Used as true cache  64-bit lines  Effective for ordinary random access  To support serial access of block of data  E.g. refresh bit-mapped screen CDRAM can prefetch data from DRAM into SRAM buffer Subsequent accesses solely to SRAM
  • 17. Read Only Memory (ROM)  Permanent storage  Nonvolatile  Microprogramming (see later)  Library subroutines  Systems programs (BIOS)  Function tables
  • 18. ROM (Read Only Memory) ROM ini sifatnya permanen, artinya program / data yang disimpan di dalam ROM ini tidak mudah hilang atau berubah walau aliran listrik di matikan. Salah satu contoh ROM adalah ROM BIOS yang berisi program dasar system komputer yang mengatur / menyiapkan semua peralatan / komponen yang ada dalam komputer saat komputer dihidupkan. Main Memory
  • 19. Types of ROM  Written during manufacture  Very expensive for small runs  Programmable (once)  PROM  Needs special equipment to program  Read “mostly”  Erasable Programmable (EPROM)  Erased by UV  Electrically Erasable (EEPROM)  Takes much longer to write than read  Flash memory  Erase whole memory electrically
  • 20. Organisation In Detail  A 16Mbit chip can be organised as 1M of 16 bit words  A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on  A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array  Reduces number of address pins  Multiplex row address and column address  11 pins to address (211=2048)  Adding one more pin doubles range of values so x4 capacity
  • 21. Refreshing  Refresh circuit included on chip  Disable chip  Count through rows  Read & Write back  Takes time  Slows down apparent performance
  • 22. Interleaved Memory  Collection of DRAM chips  Grouped into memory bank  Banks independently service read or write requests  K banks can service k requests simultaneously
  • 23. Error Correction  Hard Failure  Permanent defect  Soft Error  Random, non-destructive  No permanent damage to memory  Detected using Hamming error correcting code
  • 24. Jenis ROM Mask ROM Programmable Read Only Memory (Eraseable Programmable Read Only Memory) EPROM Electrically Erasable Programmable Read Only Memory Main Memory
  • 25. CMOS (Complementary Metal Oxide Semiconductor) Suatu memori yang khusus yang berisi data vital mengenai konfigurasi komputer dan bersifat semi-permanen. Main Memory
  • 26. Virtual Memory Teknik manajemen memori yang dikembangkan untuk kernel multitugas. Memungkinkan sebuah program harus dirancang seolah-olah hanya ada satu jenis memori, memori "virtual", yang bertindak secara langsung beralamat memori baca/tulis (RAM). Main Memory
  • 27. Refference Stalling, William, Computer Organization and Architecture, 10th Edition, Pearson, 2015 Abdurohman, Maman, Organisasi dan Arsitektur Komputer revisi ke-4, Penerbit Informatika, 2017