TCAM Design using Flash Transistors
•Download as PPTX, PDF•
0 likes•389 views
We present a Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, and a single TCAM cell utilizes 17 transistors. In contrast, our TCAM cell utilizes only 2 flash transistors, thereby significantly reducing circuit area. We are focusing mainly on the TCAM block which does fast parallel IP routing table lookup. Our flash-based TCAM (FTCAM) block is simulated in SPICE, and we show that it has a significantly lowered area compared to a CMOS based TCAM block, with a speed that can meet current (400 Gb/s) data rates that are found in the internet core.
Recommended
Recommended
More Related Content
What's hot
What's hot (18)
Viewers also liked
Similar to TCAM Design using Flash Transistors
Similar to TCAM Design using Flash Transistors (20)
Recently uploaded
Recently uploaded (20)
TCAM Design using Flash Transistors
- 1. An Area-efficient Ternary CAM Design using Floating Gate Transistors Viacheslav Fedorov Monther Abusultan Sunil P. Khatri
- 2. Key Contributions • First TCAM design using flash transistors • 2 transistors per TCAM cell (17 for CMOS) • 1 transistor per port cell (6 for CMOS) • Layout and SPICE simulations – 8 times more dense than CMOS TCAM – 1.6x less power consumption – Operates at today’s line rates (~ 400 Gb/s)
- 3. Outline • Contribution • Motivation • TCAM operation • Previous work • Our approach • Evaluation • Conclusion
- 4. Motivation • Internet backbone (core) operates at extreme speeds – 100s of Gb/s • Fast IP routers crucial to sustain the internet • Hardware Ternary Content-addressable Memory used for core routers – Enables lookup of IP addresses in parallel – Increases routing speed dramatically • Drawbacks: large area, high power consumption
- 5. IP Routing Address Interface 01001 B 01010 C 01011 C Router 1Router 2 A E C B D Address Interface 01001 D 11000 E 11001 E 01000 01001 To: 01001
- 6. • Ternary (entries can have “0”, “1” or “X”) TCAM operation Address Interface 01000 A 01001 A 01010 A 01011 A 10000 B • Content-addressable 0100001000 Address Interface 010XX A 10000 B • High-speed hardware-parallel lookups
- 7. Longest Prefix Matching • “010XX” : “010” (prefix) U “XX” (mask) • IP address might match more than one entry – “01000” matches “0100X” and “010XX” below • Select the entry with longest prefix (fewer “X”s) • Longer prefix = more specific routing information Address Interface 010XX A 0100X C 000XX D 1XXXX E 110XX B
- 8. Outline • Contribution • Motivation • TCAM operation • Previous work • Our approach • Evaluation • Conclusion
- 9. Previous work • TCAM research largely done using CMOS • Monolithically stacked TCAM – 3D stacking memory array on top of search circuitry – Programmable vias replace SRAM – 4x cell density, 3.5x dynamic power reduction – Orthogonal to our ideas • Resistive TCAM cells – Utilizing PCM and STT-MRAM technology – Up to 20x cell density – Relatively high latency (several nanoseconds) – Early stages of design
- 10. Previous work • Research on Flash devices – Device characterization – Cell program/erase optimization – Wear leveling algorithms – Do not consider using them in TCAM circuits
- 11. Outline • Contribution • Motivation • TCAM operation • Previous work • Our approach • Evaluation • Conclusion
- 12. Our approach: Overview • Routing entries stored in blocks – Fixed number of blocks for each mask length • Single LPM block • Shadow blocks – Control route flaps – Control burst updates
- 13. Our approach: TCAM Block • Address is looked up in TCAM portion of the block – 256 entries looked up in parallel, at most one matches (implemented using matchline) • Matched entry has its port memory driven out
- 14. Our approach: TCAM Row • Matchline (precharged) spans 256 TCAM cells horizontally – Large delay for any row • Split the matchline into smaller (8-bit) sections – Cascade mismatch propagation – Use keepers to speed up the lookup 256 TCAM cells Matchline
- 15. Our approach: Operation Stored “1” Stored “0” Stored “X” match
- 16. Our approach: Lookup “1” Stored “1” Stored “0” Stored “X” For lookup of “1”: a(i) = RH b(i) = RL match Match stays prechg Match pulled down Match stays prechg
- 17. Our approach: Lookup “0” Stored “1” Stored “0” Stored “X” For lookup of “0”: a(i) = RL b(i) = RH match Match stays prechgMatch pulled down Match stays prechg
- 18. Flash versus CMOS TCAM Cells 0.2v 0.7v 0.7v Flash TCAM cell CMOS TCAM cell match
- 19. Our approach: Proof of correctness Threshold and read voltages 0.6v 0.21v 0.76v 1.1v match Store ”1” Lookup ”1” Lookup ”0” Store ”0”
- 20. Our approach: Port cell 4 Flash-based Port cells CMOS Port cell (SRAM)
- 22. Our approach: Erase V Erase
- 23. Outline • Contribution • Motivation • TCAM operation • Previous work • Our approach • Evaluation • Conclusion
- 24. Evaluation • Implemented flash-based TCAM block – Emulated flash model cards (45nm from IEDM) – Developed cell layout – Raphael parasitic extraction – HSPICE simulation • Compared to CMOS implementation – Used PTM 45nm process
- 25. Evaluation • Layout pictures Flash-based TCAM cell layout Flash-based Port cell layout
- 26. Evaluation TCAM part Port Memory part Total Delay Power Delay Power Delay Power Area CMOS 218 ps 96 mW 174 ps 33 mW 393 ps 129 mW 286655 µ2 Flash 679 ps 65 mW 306 ps 14 mW 985 ps 79 mW 36130 µ2 Ratio (Flash/CMOS) 2.5x 0.6x 0.126x
- 27. Lifetime Estimation • In-house TCAM-based router simulator • RIB snapshots of a real internet router • Replayed UPDATE traces for 1 day • Assumptions (0.5in2 chip): – 1.5M FTCAM entries / 500K occupied – Updating rewrites the whole 256-entry block – Flash endurance 105 erase/program cycles – Randomized wear leveling utilized – Size of CMOS shadow: 48 blocks x 256 entries
- 28. Lifetime Estimation Routing table size breakdown 16 17 18 19 20 21 22 23 24 0 50000 100000 150000 200000 250000 300000 350000 Routing table size / updates Base Size UPDATES w/o Shadow UPDATES w/ Shadow Prefix Length NumofEntriesofFlashthatareupdated
- 29. Lifetime Estimation • 535K UPDATES to flash blocks, w/o CMOS shadow • 210K UPDATES to flash blocks, w/ CMOS shadow • Observations: – CMOS shadow blocks filter 61% UPDATES – Average time between flushes to flash blks ~ 5min – Several cases when 7 flushes in 1 second • Can support this with double-buffering – No packets are lost • Estimated TCAM lifetime is 5 years (worst case)
- 30. Conclusion • First to design a TCAM using flash transistors • Extremely high density – TCAM cell: 2 transistors vs 17 with CMOS – Port memory cell: 1 trans. vs 6 with CMOS • Area improvement 8x • Power improvement 1.64x • Exceeds current internet backbone data rates (~400 Gb/s) • > 5-year lifetime