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A Comparative Study of Delay Analysis forCarbon Nanotube and Copper based VLSI         Interconnect Models                ...
Outline•   Introduction•   Interconnect Models•   Factors affecting interconnect performance•   CNT v/s Copper•   Analytic...
Introduction  • Interconnects – these are wires connecting transistors.  • As technology scales down :                    ...
Interconnect Models                                                  Parasitic Inductance            L           Parasitic...
Factors affecting Interconnect Performance• Repeater design               →                                               ...
Limitations of Copper• Surface Scattering                         MFP of e- in Cu = 40 - 100 nm                         Po...
Carbon Nanotube (CNT)                 Future interconnect material?• Graphene sheet rolled into a tube. Formation eliminat...
CNT Model  For L< λCNT or MFP:Fundamental Resistance                       Magnetic Inductance      Kinetic InductanceRF =...
CNT v/s CuLOCAL INTERCONNECTS             ρ.l    R Cu                         small l    small R             A            ...
Analytical Delay Estimation1. Driver Interconnect Model (DIL)2. Modified Nodal Analysis (MNA) and Moment   Matching3. Unif...
1. Driver Interconnect Model (DIL)RLC interconnect driven a CMOS driver • Region 1 : During this region,                  ...
DIL Results                        COPPER                                              CNT              1.2               ...
2. Modified Nodal Analysis (MNA)Solving the above circuit through MNA, we obtain these two equations:                     ...
Moment MatchingMaclaurin expansion of the transfer function (Taylor’s expansion around s=0)The coefficients of this expans...
Moment Matching example             Rmos                R1                  L1                            R2         L2   ...
3. Unified Time Delay ModelMeindl et al. (2001 [6-9]) presented simplified delay expressions in a series of four papers. U...
Unified Time Delay                             Results                                            0.6                     ...
Comparison Of The Analytical Models                                             Percentage error (%)S.no.       Analytical...
CU v/s CNT (SPICE Simulation)Simulation parameters                                       Copper             CNTtechnology ...
Cu v/s CNT (SPICE)                   Variation Of Repeater Size / Number                                                  ...
Cu v/s CNT (SPICE)                               Variation Of Pitch                                 Copper                ...
Conclusion• In the 45 nm node, CNT bundle interconnects show significant  improvement in delay performance as compared to ...
References1.   H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, Reading, MA, 19902.   Bak...
References14.   F. Kreupl, et al., “Carbon Nanotubes in Interconnect Applications,” Microelectronic Engineering, 64 (2002)...
THANK YOU
APPENDIX: α-power law MOS modelID = 0                                                   ;        V GS       V T0          ...
APPENDIX: RC Models                                             R/3        R/3         R/3    Pi- Model• Delay of Pi-Model...
APPENDIX: Repeater insertion• Repeaters are buffers or inverters inserted at regular intervals.• RC delay is proportional ...
Repeater design (Bakoglu and Mendl) Minimum size repeaters •     W/Ldriver = 1, W/Lload = 3     Optimal repeaters         ...
Bakoglu and Meindl Model            RC Load                                                C Load                         ...
Bakoglu and Meindl…• By setting dT/dk = 0 and dT/dh = 0, “optimal” values for k and  h are obtained                     0 ...
Bakoglu and Meindl…• For long-distance interconnections, Cint is on the order of  picofarads and Co is on the order of fem...
APPENDIX: Parameters affecting      interconnect performance• Dielectric • Parallel plate equation: C = εA/ Xox• Width    ...
Parameters affecting interconnect            performance• Width                         But,  of Interconnect• Dielectric ...
Parameters affecting interconnect            performance• Diffusion Barrier   • Reduction of copper cross-sectional area• ...
Parameters affecting interconnect            performance• Dielectric                          • Aspect ratio: AR = h/w• As...
Challenges of VLSI interconnects in    deep sub-micron technologies• Surface Scattering• Grain Boundary effect            ...
[17]• The 50% delay of Y(t) is essentially the median point of the impulse response.• If H(t) is symmetric, the 50% delay ...
APPENDIX: Kinetic Inductance•   The total energy associated with electric current is    In normal wires, the energy stored...
APPENDIX: Quantum Capacitance•   To add electric charge to a quantum wire, one must add electrons to available    states a...
APPENDIX• As rise times decrease the bandwidth of the signal increase, as more no. of higher  frequency components (harmon...
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A Comparison Of Vlsi Interconnect Models

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  • Device delay improves, but Interconnect delay increases. Globallengths are not shrunk, so they getslower.
  • As interconnect length approaches MFP, or lowers down further, these effects become prominent.
  • Ballistic conduction is the unimpeded flow of charge or energy carrying particles over relatively long distances in a material.
  • CNT bundle local interconnects have larger delay than Cu due to their larger resistance.
  • Input=u(t). Output=y(t). MNA=KCL for R and C. KVL for L or voltage source.
  • if time of flight dominates, then the line behavior is inductive. Otherwise, it is a resistive line.
  • UDE can only be used to determine the trend for interconnect delay
  • delay of segments connected by the repeaters = delay of a repeater. In this case, the slow switching due to resistance is counterbalanced by the fast switching of the gates.
  • How many repeaters should we use? How large should each one be?. RC delay v/s LC delay.
  • A dielectric is an electrical insulator that may be polarized by an applied electric field. Dielectric Constant relates how much the capacitance is increased due to presence of the material.
  • Pitch remains constant : as w increases, s decreases.
  • Barriers have much higher resistivity. Materials used are Transition metal - silicon compounds: Adding Si to Ta, Ti, Mo, W yields amorphous refractory barriers with stability to 700°C. Diffusion - molecules spread from areas of high concnto areas of low concn
  • As interconnect length approaches MFP, or lowers down further, these effects become prominent.A crystal is a material whose atomsare arranged in an orderly repeating pattern. Polycrystalline are composed of many crystallites/ grains.Scatter- deviate from a straight trajectory
  • Higher order moments give more sophisticated measurement for the distribution of the impulse response.
  • Transcript of "A Comparison Of Vlsi Interconnect Models"

    1. 1. A Comparative Study of Delay Analysis forCarbon Nanotube and Copper based VLSI Interconnect Models By HARPREET SINGH BHATIA Under the supervision of MR. MAYANK K. RAI Assistant Professor, ECED DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING THAPAR UNIVERSITY, PATIALA
    2. 2. Outline• Introduction• Interconnect Models• Factors affecting interconnect performance• CNT v/s Copper• Analytical Delay Estimation• SPICE simulation- CNT v/s Copper• Conclusion
    3. 3. Introduction • Interconnects – these are wires connecting transistors. • As technology scales down : Types •Local/short •Intermediate / semiglobal •Global Local Global [1] Effect of SCALING 2 RC delay: t int = (RL)(CL) = RC.L•Density of interconnect >> Density of gates; L•Interconnects constitute the main source of Delay. Local delay: 2 t int = (R. S )(C) 2 = RC.L 2 S 2 2 2 Global: t int = (R. S )(C) L = RC.L .S
    4. 4. Interconnect Models Parasitic Inductance L Parasitic Resistance L ≈ M f( h.w L ) R = ρ.L h h.w L≈ nH/cmXox W R≈ kΩ/cm Parasitic Capacitance Cpp = ε.w.l Xox C= Cpp +Cfringe RLC Model C≈ pF/cm RC model
    5. 5. Factors affecting Interconnect Performance• Repeater design → W/L driver n, W/L load 3n →• Dielectric C A k 0 X ox• Pitch Pitch = w + s• Length R RS l But, C pp ε dielectric hl w s• Aspect Ratio h .l AR C w AR
    6. 6. Limitations of Copper• Surface Scattering MFP of e- in Cu = 40 - 100 nm Polycrystalline are composed of• Grain Boundary many crystallites/ grains. e- s scatter at Grain-boundaries. effect Increase in ρo- from 1.9μΩ-cm to 4.9μΩ-cm @ 45nm [25]• Barrier Width
    7. 7. Carbon Nanotube (CNT) Future interconnect material?• Graphene sheet rolled into a tube. Formation eliminates dangling bonds• Single Wall CNT (SWCNT) and Multiple Wall CNT (MWCNT) Advantages CNT Cu ProblemsMean free path (nm) @ room >1000 40 1. High resistance ~6.45kΩ temp 2. Contact resistance~100ΩMax current density (A/cm2) >1x1010 ~1x106  Therefore, the NEED FOR CNT BUNDLEThermal conductivity (W/mK) 5800 385 3. Lack of control on chirality
    8. 8. CNT Model For L< λCNT or MFP:Fundamental Resistance Magnetic Inductance Kinetic InductanceRF = h/4e2 = 6.45 KΩ LM = μ ln(y/d) LK = h/4e2vFSince each nanotube has 2π •Only for L< λCNTfour conducting •Not observed upto 10GHz freqchannels in parallel(N=4) [16] Ground-Plate Quantum Capacitance Capacitance CQ = 2e2 CE = 2πε hvF ln(y/d) Quantum electrostatic energy stored in the nanotube when it carries current. 4 CQ for 4 channels →
    9. 9. CNT v/s CuLOCAL INTERCONNECTS ρ.l R Cu small l small R A h L h R CNT For L<Lo R CNT 2 =6.45 KΩ 4e 2 L0 4eGLOBAL INTERCONNECTS For Copper: large l large R Cu R CNT grows more slowly than Copper because Rcontact is a constant resistance
    10. 10. Analytical Delay Estimation1. Driver Interconnect Model (DIL)2. Modified Nodal Analysis (MNA) and Moment Matching3. Unified Time Delay Model
    11. 11. 1. Driver Interconnect Model (DIL)RLC interconnect driven a CMOS driver • Region 1 : During this region, the nMOS is cut off. uses α-power law id iL 0 MOS model → • Region 2 : During this region, the nMOS operates in saturation t in id iL 0 V in V DD τ • Region 3 : During this region V in V DD and nMOS is still in saturation • Region 4 : During this region, [20] and nMOS transistor operates in linear region.
    12. 12. DIL Results COPPER CNT 1.2 1.2 1 1 0.8 Voltage (V) 0.8Voltage (V) 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 0.912 1.9 2.9 0 0.912 1.9 time (ns) spice time (ns) spice Analytical Analytical
    13. 13. 2. Modified Nodal Analysis (MNA)Solving the above circuit through MNA, we obtain these two equations: C 0 v c (t) Y E M x (t) = - G x (t) + P u (t) where, M = x (t) = G = T 0 L i L (t) -E Ry (t) Q x (t)Using Laplace transform we solve the equations in s-Domain y(s) -1 -1 1H (s) = = Q (1 + s A ) B where, A G M B G P u(s)Performing the inversion on matrix (1 + s A ) is complicated. Reduction is done by MatrixApproximation (PVL and Arnoldi approximation)
    14. 14. Moment MatchingMaclaurin expansion of the transfer function (Taylor’s expansion around s=0)The coefficients of this expansion are known as central moments Focusing on the first moment If y(t) is a step function, then this voltage-time area is equal to its 50% delay →
    15. 15. Moment Matching example Rmos R1 L1 R2 L2 6.631k 1037.82k 884.5pH =R1 =L1 + C2 Vs Cmos C1 1V 2.1fF =C1 0.0053pF -Using MNA and PVL approximation, we calculate the transfer function H(s) upto 3 terms: -8 -16 2 H ( s ) = 1 - (1.656 × 10 ) s + (2.743 × 10 )sUsing Moment Matching of Maclaurin Series, we calculate the first moment m(1) =16.56 ns.i.e. 50 % delay = 16.56 ns.SPICE Simulation Results show this to be 13.59 ns. (error of 21.86 %.)
    16. 16. 3. Unified Time Delay ModelMeindl et al. (2001 [6-9]) presented simplified delay expressions in a series of four papers. Unified Time Delay for distributed RLC lines t d = max ( t d,rlc , t d,rc ) 2 t d = [max( t f ,0 .377 rcL + 0 .693 R tr cL ) ] + [ 0 .693 .C L ( rL+ 0 .65 R tr + 0 .36 Z c ) ] Unified Time Delay for repeater insertion t d = max ( t d,rlc _ rep , t d,rc _ rep ) 2 rcL R c cL t d = [max( t f , 0 .377 + 0 .693 ) ] + [ 0 .693 .C C ( hrL+ 0 .65 kR c + 0 .36 hkZ c )] k h
    17. 17. Unified Time Delay Results 0.6 0.5 0.4Delay for Cu interconnect Delay (ns) 0.3(for (W/L)driver= 80) Analytical Delay 0.2 Exp. Delay 0.1 0 2 4 6 8 10 12 14 16 Repeaters 8 7 6Delay for CNT bundle (for 5 Delay (ns)(W/L)driver= 80) 4 Analytical Delay 3 Exp. Delay 2 1 0 2 4 6 8 10 12 14 16 Repeaters
    18. 18. Comparison Of The Analytical Models Percentage error (%)S.no. Analytical Model CNT interconnect Copper interconnect Driver Interconnect Load 1. (DIL) 6.63% 10.04% 2. MNA & moment matching 20.86% 21.86% 3. Unified Time Delay Model 127% 86.30%
    19. 19. CU v/s CNT (SPICE Simulation)Simulation parameters Copper CNTtechnology 45 nm 45 nmVDD 1V 1Vlength (L) of interconnect 1000 um (global) 1000 um (global)width (w) of interconnect 102.5 nm 102.5 nmspacing (s) between interconnects 102.5 nm 102.5 nmthickness (h) of global interconnect 235.75 nm 235.75 nmresistivity (relative) 2.45 Ω-cm -oxide thickness (tOX) 215.25 nm 215.25 nmεOX (relative) 2.45 2.45Load capacitance 50fF 50fFfrequency 0.1 GHz 0.1 GHz
    20. 20. Cu v/s CNT (SPICE) Variation Of Repeater Size / Number Repeater driver widths 1.3 W/L(n) 1.2 40 1.1 80Delay (ns) 1 0.9 100 0.8 110 0.7 0.6 120 2 4 6 8 10 12 14 16 Repeaters
    21. 21. Cu v/s CNT (SPICE) Variation Of Pitch Copper CNT technology 45 nm 45 nm frequency 0.1 GHz 0.1 GHz (W/L)driver 110 110 1.4 1.2 1Delay (ns) 0.8 1.5:0.5 0.6 01:01 0.4 0.5:1.5 0.2 0 2 4 6 8 10 12 14 16 Repeaters
    22. 22. Conclusion• In the 45 nm node, CNT bundle interconnects show significant improvement in delay performance as compared to copper interconnects for the following cases- – CNT offers a better reduction in delay when the pitch ratio is 1:1. – CNT gives a better delay reduction than copper when repeater driver transistor W/L ratio above 80 (29.4 % to 36.43 %).• When estimating the delay analytically, a tradeoff needs to be made between the computational efficiency and accuracy. – Unified Time Delay Model has simplified expressions but higher inaccuracies. – Driver Interconnect Model (DIL) is very accurate, but requires higher computational efficiency.
    23. 23. References1. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, Reading, MA, 19902. Bakoglu, H.B. and Meindl, J.D. “Optimal interconnection circuits for VLSI”, IEEE Transactions on Electron Devices, (1985), Vol. ED-32 No. 5, pp. 903-9.3. P. Kapur, J.P. Vittie and K. C. Saraswat, “Technology and Reliability Constrainted Future Copper Interconnects-Part I” IEEE Transactions on Electron Devices, (2002)4. El-Moursy, M.A. and Friedman, E.G. “Optimum wire sizing of RLC interconnect with repeaters”, Integration, the VLSI journal (2004)5. Bakoglu, H.B. and Meindl, J.D. “Optimal interconnection circuits for VLSI”, IEEE Transactions on Electron Devices, (1985)6. Davis, J.A., Meindl, J.D., Compact distributed RLC interconnect models—Part I: single line transient, time delay and overshoot expressions, IEEE Trans. Electron Dev. 47 (2000) 2068–2077.7. J.A. Davis, J.D. Meindl, Compact distributed RLC interconnect models—Part II: coupled line transient expressions and peak crosstalk in multilevel interconnect networks, IEEE Trans. Electron Dev. 47 (2000) 2078–2087.8. R. Venkatesan, J.A. Davis, J.D. Meindl, Compact distributed RLC interconnect models—Part III: transients in single and coupled lines with capacitive load termination, IEEE Trans. Electron Dev. 50 (2003) 1081–1093.9. R. Venkatesan, J.A. Davis, J.D. Meindl, Compact distributed RLC interconnect models—Part IV: unified models for time delay, crosstalk, and repeater insertion, IEEE Trans. Electron Dev. 50 (2003) 1094–1102.10. Chandel, R., Sarkar, S. and Agarwal, R.P. “Repeater insertion in global interconnects in VLSI circuits” (2005).
    24. 24. References14. F. Kreupl, et al., “Carbon Nanotubes in Interconnect Applications,” Microelectronic Engineering, 64 (2002)15. Sakurai, T. and Newton, A.R. “Alpha power law MOSFET model and its applications to CMOS inverter delay and other formulas”, IEEE Journal of Solid State Circuits, (1990)16. P J Burke, Luttinger Liquid Theory as a Model of the Gigahertz Electrical Properties of Carbon nanotubes ; IEEE Transactions on Nanotechnology, Vol 1, no 3, 2002.17. C. Ho, , A.E. Ruehli, P. A. Brennan, The Modified Nodal Approach to Network Analysis, IEEE Transactions on Circuits and Systems, 197518. A.B. Kahng, S. Muddu, Efficient gate delay modeling for large interconnect loads, IEEE Multi-Chip Module Conf. (1996)19. Y. I. Ismail and E. G. Friedman, “Sensitivity of Interconnect Delay to On-Chip Inductance”, ISCAS (2000)20. B.K. Kaushik et al., S. Sarkar, R.P. Agarwal, Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load, INTEGRATION, the VLSI journal 40, 2007, pp. 394–405.21. Shyh-Chyi Wong, Winbond TSM, “Estimation of Wire Parameters” IEEE, Proc. Feb 2000.22. C. Thiruvenkatesan, J. Raja, “Studies on the Application of Carbon Nanotube as Interconnects for Nanometric VLSI Circuits”, ICETET-09, (2009)25. W. Steinhogl, et al., “Size-dependent Resistivity of Metallic Wires in the Mesoscopic Range,” , (2002).
    25. 25. THANK YOU
    26. 26. APPENDIX: α-power law MOS modelID = 0 ; V GS V T0 : cutoff region ( /2)I D = k 1 (V GS - V T0 ) .V DS ; V DS < V (DS- sat) : linear regionI D = k S (V GS - V T0 ) ; V DS V (DS- sat) : saturation region channel length is decreased lateral electric field EY increases drift velocity vd α electric field => for electric fields of E >105 V/cm, velocity saturates vd(sat) = 107 cm/s saturation-mode current is no longer a quadratic function of VGS ←
    27. 27. APPENDIX: RC Models R/3 R/3 R/3 Pi- Model• Delay of Pi-Model C/2 C/2 = RC/3+RC/6 = RC/2 agrees with distributed model RC.• 3-segment pi-model is accurate to 3% in simulation• L-model needs 100 segments for same accuracy!• Pi Model is often used in Spice instead of large number of segments as a reasonable approximation of distributed RC. ←
    28. 28. APPENDIX: Repeater insertion• Repeaters are buffers or inverters inserted at regular intervals.• RC delay is proportional to l2• Now, Delay linearly proportional to l (Bakoglu and Meindl Model →) 2 Td 2 . 3 R o C int R int C o Wire Length: l Driver Receiver Td 2 . 3 R o C int N Segments Segment l/N l/N l/N ← Driver Repeater Repeater Repeater Receiver
    29. 29. Repeater design (Bakoglu and Mendl) Minimum size repeaters • W/Ldriver = 1, W/Lload = 3 Optimal repeaters •Increasing size of repeaters to improve propagation time •Increase W/L by h, R becomes Ro/h, C becomes Co.h •Area penalty + Power Penalty Cascaded drivers •Sequence of drivers that increase gradually in size •Used to drive large capacitive loads •Power penalty ←
    30. 30. Bakoglu and Meindl Model RC Load C Load Ro Rint, Cint For a wire with k repeaters each of size h times minimum size Co inverter is given by: Ro C int R int C intT 50 % k 0 .7 hC o 0 .4 0 . 7 hC o h k k k
    31. 31. Bakoglu and Meindl…• By setting dT/dk = 0 and dT/dh = 0, “optimal” values for k and h are obtained 0 . 4 R int C int R o C int k h 0 .7 R o C o R int C o• Substituting these back, delay is given by 2 Td 2 . 3 R o C int R int C o
    32. 32. Bakoglu and Meindl…• For long-distance interconnections, Cint is on the order of picofarads and Co is on the order of femptofarads, and Rint and R, have values around kilohms; Therefore, RoCint>>RintCo, and the delay expression can be further simplified to T =2.3RoCint• As a result, repeaters can effectively "transform" the RC interconnection load into a capacitive load.• Delay of a capacitive load is linearly proportional to l. ←
    33. 33. APPENDIX: Parameters affecting interconnect performance• Dielectric • Parallel plate equation: C = εA/ Xox• Width • Dielectric constant of Interconnect – ε= kε0 – ε0 = 8.85 x 10-14 F/cm• Diffusion Barrier k = 3.9 for SiO2 – • To reduce capacitance, we need to use low-• Length k dielectrics• Pitch – k 3 (or less)• Aspect Ratio • But, low-k materials have lower thermal conductivity • leads to significant metal-temperature
    34. 34. Parameters affecting interconnect performance• Width But, of Interconnect• Dielectric Pitch = w + s• Diffusion Barrier• Length• Pitch• Aspect Ratio ←
    35. 35. Parameters affecting interconnect performance• Diffusion Barrier • Reduction of copper cross-sectional area• Dielectric – Cu atoms diffuse into silicon and damage FETs• Width – Must be surrounded by a diffusion barrier of Interconnect – So, ρ increases• Length • Barrier thickness doesn’t scale rapidly as the interconnect dimensions because of• Pitch reliability constraints• Aspect Ratio
    36. 36. Parameters affecting interconnect performance• Dielectric • Aspect ratio: AR = h/w• Aspect Ratio – Old processes had AR << 1 – Modern processes have• Width AR 2 • h>>w of Interconnect • C = ε.(wl)/h• Diffusion Barrier • R = ρl/tw• Pitch• Length Global interconnect lengths remain the same.
    37. 37. Challenges of VLSI interconnects in deep sub-micron technologies• Surface Scattering• Grain Boundary effect MFP of e- in Cu = 40 - 100 nm• Barrier Width These effects lead to the increase in ρo- increases from 1.9μΩ-cm to 4.9μΩ-cm @ 45nm [25] →
    38. 38. [17]• The 50% delay of Y(t) is essentially the median point of the impulse response.• If H(t) is symmetric, the 50% delay is accurately –m(1) (the first moment of the impulse response). This is Elmore delay. ←
    39. 39. APPENDIX: Kinetic Inductance• The total energy associated with electric current is In normal wires, the energy stored in the magnetic field is significantly larger than the kinetic energy of electrons, and the second integral is negligible.• Kinetic inductance per unit length is given by• Reactive impedance is always going to be negligible compared to its resistance. Resistance per unit length is where τ is the average collision time for carriers.• Kinetic inductance for a carbon nanotube becomes important as the mean free path of electrons can be very large. ←
    40. 40. APPENDIX: Quantum Capacitance• To add electric charge to a quantum wire, one must add electrons to available states above the Fermi level (Pauli Exclusion Principle). The required energy to add electric charge Q to a quantum wire is where the first term is the energy stored in the electric field (CE is the electrostatic capacitance) and e is electron charge.• By equating this energy to an effective capacitance, the expression for the quantum capacitance (per unit length) is obtained as shown and has a value in the order of 100 aF/m, in the same order of the electrostatic capacitance of a typical wire above a ground plane.• As a CNT has four conducting channels as described in the previous sub- section, the effective quantum capacitance resulting from four parallel capacitances cQ is given by 4cQ. ←
    41. 41. APPENDIX• As rise times decrease the bandwidth of the signal increase, as more no. of higher frequency components (harmonics) need to be accompanied into the signal to achieve this rise-time.• approximation: BW = 0.35/RT• So, the effective frequency of a 100 MHz wave is 1GHz if only 10 harmonics are taken.
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