Blackfin Processor Core Architecture Part 2

Blackfin Processor Core Architecture Part 2 ,[object Object]

Module Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

The Blackfin Processor Core ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

The Arithmetic Unit ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Data Registers ,[object Object],[object Object],[object Object],[object Object]

16-Bit ALU Operations - Examples ,[object Object],These operations effectively execute in a single cycle.

32-Bit ALU Operations—Examples Single 32-bit addition Dual 32-bit operation These operations effectively execute in a single cycle.

Dual MAC Operations - Example ,[object Object],Both MACs can be used at the same time to double the MAC throughput. The same two 32-bit input registers must be used (R2 and R3 in this example). These operations effectively execute in a single cycle.

Barrel Shifter ,[object Object],[object Object],[object Object],[object Object],[object Object]

8-Bit ALU Operations ,[object Object],[object Object],[object Object],[object Object]

Additional Arithmetic Instructions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

The Addressing Unit ,[object Object],[object Object],[object Object]

Address Registers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Addressing ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Circular Buffer Example ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

The Sequencer ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Sequencer Registers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Instruction Pipeline ,[object Object]

Instruction Pipeline ,[object Object],[object Object]

Blackfin Event Handling ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

System and Core Interrupts (ADSP-BF533 example)

Variable Instruction Lengths ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Instruction Packing ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

16-bit FIR Filter Example - 0.5 cycles per tap

Additional Resource ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Newark Farnell

Blackfin Processor Core Architecture Part 2

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Blackfin Processor Core Architecture Part 2