Structural vhdl

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Structural VHDL design of a 1-bit Full Adder. By Tom Pestak (Wright State University Dept of Electrical Engineering)

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Structural vhdl

  1. 1. Structural VHDLof1-Bit Full AdderEE160Wright State University<br />
  2. 2. Structural FA<br />The Top Level Design (entity) of a 1-bit Full-Adder looks like this:<br />A<br />B<br />Cout<br />Cin<br />FA_1<br />Sum <br /><ul><li>There are 5 ports, which all appear in the entity declaration.</li></ul>entity FA_1 is <br /> port(A,B,Cin : in std_logic;<br /> Sum, Cout : out std_logic);<br />end;<br />end; <br />
  3. 3. Structural FA<br />At this point we only have an empty box with ports. We need to specify the internal details of our entity. <br />Sum <br />A<br />B<br />Cout<br />Cin<br />FA_1<br /><ul><li>The design of a full-adder uses the following components: XOR_2 gates, AND_2 gates, and OR_2 gates. Each component has already been created in the EE160_lib.vhd file.</li></li></ul><li>Structural FA<br />The XOR_2 Gate<br />The AND_2 Gate<br />The OR_2 Gate<br />-- OR_2 Gate Definition<br />library IEEE;<br /> use IEEE.STD_LOGIC_1164.ALL;<br />entity OR_2 is <br /> port(A,B : in std_logic;<br /> Z : out std_logic);<br />end; <br />architecture BEHAV of OR_2 is<br />begin<br /> Z <= A or B;<br />end; <br />-- AND_2 Gate Definition<br />library IEEE;<br /> use IEEE.STD_LOGIC_1164.ALL;<br />entity AND_2 is <br /> port(A,B : in std_logic;<br /> Z : out std_logic);<br />end; <br />architecture BEHAV of AND_2 is<br />begin<br /> Z <= A and B;<br />end; <br />-- XOR_2 Gate Definition<br />library IEEE;<br /> use IEEE.STD_LOGIC_1164.ALL;<br />entity XOR_2 is <br /> port(A,B : in std_logic;<br /> Z : out std_logic);<br />end; <br />architecture BEHAV of XOR_2 is<br />begin<br /> Z <= A xor B;<br />end; <br />A<br />A<br />A<br />XOR_2<br />AND_2<br />OR_2<br />Z<br />B<br />B<br />B<br />Z<br />Z<br />
  4. 4. In structural modeling, the internal details of an entity are specified by an architecture body that contains interconnected components.<br />For the FA example, we must connect our XOR_2, AND_2, and OR_2 gates appropriately, using intermediate signals where necessary.<br />The next slide shows how the components must be connected together. The yellow wires are necessary intermediate signals.<br />Structural FA<br />
  5. 5. Structural FA<br />FA_1<br />A<br />XOR_2<br />A<br />sig(0)<br />A<br />XOR_2<br />Sum <br />B<br />Z<br />B<br />B<br />Z<br />Cin<br />A<br />AND_2<br />B<br />sig(1)<br />Z<br />A<br />Cout<br />OR_2<br />B<br />Z<br />A<br />AND_2<br />sig(2)<br />B<br />Z<br />
  6. 6. Structural FA<br />The left side is the component declaration, the right side is component instantiation. The bolded ports are the component’s ports. The commented U4 shows implicit connection as opposed to explicit, which is functionally equivalent.<br />begin<br /> U0: XOR_2 port map(A=>A, B=>B, Z=>sig(0));<br />U1: XOR_2 port map(A=>sig(0), B=>Cin, Z=>Sum);<br />U2: AND_2 port map(A=>Cin, B=>sig(0), Z=>sig(1));<br />U3: AND_2 port map(A=>A, B=>B, Z=>sig(2));<br />U4: OR_2 port map(A=>sig(1), B=>sig(2), Z=>Cout);<br />--U4: OR_2 port map(sig(1), sig(2), Cout);<br />--functionally the same <br />end; <br />architecture STRUCT of FA_1 is<br /> component XOR_2<br />port(A,B:instd_logic; Z:out std_logic);<br /> end component;<br /> component AND_2<br />port(A,B:instd_logic; Z:out std_logic);<br /> end component;<br /> component OR_2<br />port(A,B:instd_logic; Z:out std_logic);<br /> end component;<br /> signal sig : std_logic_vector(2 downto 0);<br />
  7. 7. Now that you’ve written the code for the FA_1, you can use it as a component in an FA_4, or an add/subtract circuit.<br />Remember that you can connect the ports of an entity to the ports of a component (and vice versa), but you need to create local signals to connect a component to another component within an entity.<br />Structural FA<br />

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