SlideShare a Scribd company logo
1 of 7
Download to read offline
Chapter 3- Logic Gates II PUC, MDRPUC, Hassan
1 | P a g e
Chapter-3
LOGIC GATES
 Introduction:
 Gate: A Gate is a simply an electronic circuit which operates on one or more input signals and
always produces an output signal.
 Gates are digital (two state) circuits because the input and output signals are either low voltage (0) or
high voltage (1).
 Gates are often called logic circuits because they can be analyzed with Boolean algebra.
 Gates are classified into two types:
 Basic Gates:
 NOT Gate:
 A NOT gate has only one input and one output.
 The output state is always the opposite of the input state.
 A NOT Gate is also called as Inverter gate, because the output is not same as the input.
 The output is sometimes called the complement (opposite) of the input.
 The logical symbol and the truth table of NOT gate are given below.
X X
 OR Gate:
 A OR gate has two or more input signal but only one output signal.
 If any of the input signals is 1 (high), then the output is 1 (high).
 The logical symbol for two-input OR gate and the truth table is given below.
X
0 1
1 0
Logic gates
Basic Gates Derived Gates
AND OR NOR NAND XOR
NOT XNOR
Chapter 3- Logic Gates II PUC, MDRPUC, Hassan
2 | P a g e
X F = X + Y
Y
 AND Gate:
 A AND gate has two or more input signal but only one output signal.
 When all the input signals are 1 (high), the output is 1 (high), otherwise the output is 0.
 The logical symbol for two-input AND gate and the truth table is given below.
X F = X .Y
Y
 NOR Gate:
 A NOR gate has two or more input signal but only one output signal.
 The NOR gate is a complemented of OR gate.
 The output of NOR gate will be 1 only when all inputs are 0 and output will be 0 if any input
represents a 1.
 NOR is short form of NOT-OR.
 The symbol is used to represent a NOR operation. So X + Y can be written as X NOR Y or X Y.
 The logical structure shows an OR gate and NOT gate. For input X and Y, the output of the OR gate
will be X+Y which is fed as input to the NOT gate. So the output of NOR gate is given by X + Y
which is equal to X . Y
X F = X + Y F = X + Y
Y
 The logical symbol for two-input NOR gate and the truth table is given below.
X F = X + Y
Y
X Y F = X+Y
0 0 0
0 1 1
1 0 1
1 1 1
X Y F = X.Y
0 0 0
0 1 0
1 0 0
1 1 1
X Y Z F = + +
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
X Y F = +
0 0 1
0 1 0
1 0 0
1 1 0
Chapter 3- Logic Gates II PUC, MDRPUC, Hassan
3 | P a g e
 NAND Gate:
 A NAND gate has two or more input signal but only one output signal.
 The NAND gate is a complemented of AND gate.
 The output of NAND gate will be 0 only when all inputs are 1 and output will be 0 if any input
represents a 0.
 NAND is short form of NOT-AND.
 The symbol is used to represent a NOR operation. So X . Y can be written as X NAND Y or X Y.
 The logical structure shows an AND gate and NOT gate. For input X and Y, the output of the OR
gate will be X .Y which is fed as input to the NOT gate. So the output of NAND gate is given by
X . Y which is equal to X + Y
X F = X . Y F = X . Y
Y
 The logical symbol for two-input NAND gate and the truth table is given below.
X F = X . Y
Y
 XOR (Exclusive-OR) Gate:
 An exclusive-OR has two or more input signal but only one output signal.
 Exclusive-OR gate is different form of OR gate.
 Exclusive-OR gate produces output 1 for only those input combinations that have odd number of 1’s.
 The output is 0 if there are even number of 1’s in the input.
 The output is 1 if there are odd number of 1’s in the input.
 In Boolean algebra, ϴ sign stands for XOR operation. Thus X XOR Y can be written as XϴY
 If the output is given by:
F = X ϴ Y
X Y F = .
0 0 1
0 1 1
1 0 1
1 1 0
X Y Z F = . .
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Chapter 3- Logic Gates II PUC, MDRPUC, Hassan
4 | P a g e
F = X Y + X Y
 The XOR gate has a symbol similar to OR gate, except the additional curved line of the input side.
X F = X ϴ Y = X Y + X Y
Y
 The following truth table illustrates XOR operation for 2 and 3 inputs.
 XNOR (Exclusive-NOR) Gate:
 The XNOR gate is complement of XOR gate.
 The output of XNOR is 1 only when the logic values of both X and Y is same i.e. either both are
equal to 1 or both are 0.
 Its output is 0 when its inputs are different.
 In Boolean algebra, ʘ sign stands for XNOR operation. Thus X XNOR Y can be written as X ʘ Y
 If the output is given by:
F = X ʘ Y
F = XY + XY
 The XNOR gate has a symbol similar to NOR gate, except the additional curved line of the input side.
X F = X ʘ Y = XY + X Y
Y
 The following truth table illustrates XOR operation for 2 and 3 inputs.
Number
Of 1’s
Input Output
X Y F = X ϴ Y
EVEN 0 0 0
ODD 0 1 1
ODD 1 0 1
EVEN 1 1 0
Number
of 1’s
X Y Z F = X ϴ Y ϴ Z
EVEN 0 0 0 0
ODD 0 0 1 1
ODD 0 1 0 1
EVEN 0 1 1 0
ODD 1 0 0 1
EVEN 1 0 1 0
EVEN 1 1 0 0
ODD 1 1 1 1
Number
Of 1’s
Input Output
X Y F = X ʘ Y
EVEN 0 0 1
ODD 0 1 0
ODD 1 0 0
EVEN 1 1 1
Number
of 1’s
X Y Z F = X ʘ Y ʘ Z
EVEN 0 0 0 1
ODD 0 0 1 0
ODD 0 1 0 0
EVEN 0 1 1 1
ODD 1 0 0 0
EVEN 1 0 1 1
EVEN 1 1 0 1
ODD 1 1 1 0
Chapter 3- Logic Gates II PUC, MDRPUC, Hassan
5 | P a g e
 Universal Gate (NAND & NOR):
 Universal gate is a gate using which all the basic gates can be designed.
 NAND and NOR gate re called as Universal Gates, because all the Boolean functions can also be
implemented using these two gates.
 NAND and NOR gates are more popular as these are less expensive and easier to design.
 Realization of all basic gates using NAND gate:
 NAND to NOT:
 In the figure we have two input NAND gate whose inputs are purposely connected together so that
the same input is applied to both.
F = X . X = X
X
 From the diagram X NAND X = X . X
= X + X // DeMorgan’s 2nd
Theorem
= X X + X = X
= Inverted Input = NOT gate
 NAND to AND:
 In the figure we have two NAND gates connected so that the AND operations is performed.
 NAND gate 2 is used as a NOT gate.
X F1 = X . Y F2 = X. Y = X.Y
Y
 From the diagram X NAND Y =F1= X . Y
F2 = F1 . F1
= F1 + F1 // DeMorgan’s 2nd
Theorem
= X. Y X + X = X
F2 = X.Y
= AND gate
 NAND to OR:
 The OR operation can be implemented using NAND gates connected as shown in figure.
 NAND gate 1 and NAND gate 2 are used as NOT to invert the inputs.
F1 = X
X
F3 = X . Y = X + Y
F2 = Y
Y
Chapter 3- Logic Gates II PUC, MDRPUC, Hassan
6 | P a g e
 From the diagram X NAND Y
F1 = X . X = X + X = X
F2 = Y . Y = Y + Y = Y
F3 = F1 . F2
= F1 + F2 // DeMorgan’s 2nd
Theorem
= X + Y X = X and Y = Y
F3 = X +Y
= OR gate
 Realization of all basic gates using NOR gate:
 NOR to NOT:
 Figure shows that NOR gate with its inputs connected together behaves as a NOT gate.
F = X + X = X
X
 From the diagram X NOR X = X + X
= X . X // DeMorgan’s 1st
Theorem
= X X . X = X
= Inverted Input = NOT gate
 NOR to AND:
 The AND operation can be implemented with NOR gate as shown in figure. Here NOR gate 1 and
NOR gate 2 are used as NOT gate to invert inputs.
F1 = X
X
F3= X + Y = X.Y
F2 = Y
Y
 From the diagram X NOR Y
F1 = X + X = X . X =X
F2 = Y + Y = Y . Y =Y
F3 = F1 + F2
= F1 . F2 // DeMorgan’s 1st
Theorem
= X . Y X = X and Y = Y
F3 = X.Y
= AND gate
Chapter 3- Logic Gates II PUC, MDRPUC, Hassan
7 | P a g e
 NAND to OR:
 In the figure two NOR gates are arranged so that the OR operation is performed.
 NOR gate 2 is used as NOT gate.
X F1 = X + Y F2 = X + Y = X + Y
Y
 From the diagram X NOR Y
F1 = X + Y
F2 = F1 + F1
F2 = F1 . F1 // DeMorgan’s 1st
Theorem
= F1
= X + Y X = X
F2 = X +Y
= OR gate
 Designing of Logic Circuit using all basic gates :
 Designing of Logic Circuit using NAND and NOR gates:
CHAPTER – LOGIC GATES BLUE PRINT
VSA (1 marks) LA (3 Marks) - Total
01 Question 01 Question - 02 Questions
Question No 1 Question No 20 - 04 Marks

More Related Content

Similar to chapter-3-logic-gates.pdf

Similar to chapter-3-logic-gates.pdf (20)

basic logic gates
 basic logic gates basic logic gates
basic logic gates
 
STE 10 Logic gates.pptx
STE 10 Logic gates.pptxSTE 10 Logic gates.pptx
STE 10 Logic gates.pptx
 
assignment_mathematics.pptx
assignment_mathematics.pptxassignment_mathematics.pptx
assignment_mathematics.pptx
 
logic gates
logic gates logic gates
logic gates
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates. Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
 
INTRODUCTION OF LOGIC GATES
INTRODUCTION OF LOGIC GATESINTRODUCTION OF LOGIC GATES
INTRODUCTION OF LOGIC GATES
 
Digital Logic Gates .pptx
Digital Logic Gates .pptxDigital Logic Gates .pptx
Digital Logic Gates .pptx
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Chap 3
Chap 3Chap 3
Chap 3
 
BASIC LOGIC GATES.pdf
BASIC LOGIC GATES.pdfBASIC LOGIC GATES.pdf
BASIC LOGIC GATES.pdf
 
Logical Gates
Logical GatesLogical Gates
Logical Gates
 
Chapter 3_Logic Gates (EEEg4302).pdf
Chapter 3_Logic Gates (EEEg4302).pdfChapter 3_Logic Gates (EEEg4302).pdf
Chapter 3_Logic Gates (EEEg4302).pdf
 
Logic gates i & ii
Logic gates i & iiLogic gates i & ii
Logic gates i & ii
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Digital logic
Digital logicDigital logic
Digital logic
 
12733771.ppt
12733771.ppt12733771.ppt
12733771.ppt
 
Logic gates 07 11-2014
Logic gates 07 11-2014Logic gates 07 11-2014
Logic gates 07 11-2014
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Logic gates digital electronics
Logic gates digital electronicsLogic gates digital electronics
Logic gates digital electronics
 

More from study material

chapter-16-internet-and-open-source-concepts.pdf
chapter-16-internet-and-open-source-concepts.pdfchapter-16-internet-and-open-source-concepts.pdf
chapter-16-internet-and-open-source-concepts.pdf
study material
 

More from study material (20)

II PUC Reduced syllabus(NCERT ADOPTED SUBJECTS).pdf
II PUC Reduced syllabus(NCERT ADOPTED SUBJECTS).pdfII PUC Reduced syllabus(NCERT ADOPTED SUBJECTS).pdf
II PUC Reduced syllabus(NCERT ADOPTED SUBJECTS).pdf
 
12th English Notes.pdf
12th English Notes.pdf12th English Notes.pdf
12th English Notes.pdf
 
Organic_Chemistry_Named_Reaction_inDetail_by_Meritnation.pdf
Organic_Chemistry_Named_Reaction_inDetail_by_Meritnation.pdfOrganic_Chemistry_Named_Reaction_inDetail_by_Meritnation.pdf
Organic_Chemistry_Named_Reaction_inDetail_by_Meritnation.pdf
 
chem MCQ.pdf
chem MCQ.pdfchem MCQ.pdf
chem MCQ.pdf
 
pue alcholn ethers.pdf
pue alcholn ethers.pdfpue alcholn ethers.pdf
pue alcholn ethers.pdf
 
2023 Physics New Pattern
2023 Physics New Pattern 2023 Physics New Pattern
2023 Physics New Pattern
 
PHY PUC 2 Notes-Electromagnetic waves
PHY PUC 2 Notes-Electromagnetic wavesPHY PUC 2 Notes-Electromagnetic waves
PHY PUC 2 Notes-Electromagnetic waves
 
PHY PUC 2 Notes-Alternating current
PHY PUC 2 Notes-Alternating currentPHY PUC 2 Notes-Alternating current
PHY PUC 2 Notes-Alternating current
 
PHY PUC 2 Notes Electromagnetic induction
PHY PUC 2 Notes Electromagnetic inductionPHY PUC 2 Notes Electromagnetic induction
PHY PUC 2 Notes Electromagnetic induction
 
PHY PUC 2 NOTES:- MAGNETISM AND MATTER
PHY PUC 2 NOTES:- MAGNETISM AND MATTERPHY PUC 2 NOTES:- MAGNETISM AND MATTER
PHY PUC 2 NOTES:- MAGNETISM AND MATTER
 
PHY PUC 2 MOVING CHARGE AND MAGNETISM
PHY PUC 2 MOVING CHARGE AND MAGNETISMPHY PUC 2 MOVING CHARGE AND MAGNETISM
PHY PUC 2 MOVING CHARGE AND MAGNETISM
 
PHY CURRENT ELECTRICITY PUC 2 Notes
PHY  CURRENT ELECTRICITY PUC 2 NotesPHY  CURRENT ELECTRICITY PUC 2 Notes
PHY CURRENT ELECTRICITY PUC 2 Notes
 
physics El.potential & capacitance notes
physics El.potential & capacitance notesphysics El.potential & capacitance notes
physics El.potential & capacitance notes
 
important question of current electricity
important question of current electricityimportant question of current electricity
important question of current electricity
 
09.Ray optics.pdf
09.Ray optics.pdf09.Ray optics.pdf
09.Ray optics.pdf
 
01 Electric Fieeld and charges Notes.pdf
01 Electric Fieeld and charges Notes.pdf01 Electric Fieeld and charges Notes.pdf
01 Electric Fieeld and charges Notes.pdf
 
chapter-4-data-structure.pdf
chapter-4-data-structure.pdfchapter-4-data-structure.pdf
chapter-4-data-structure.pdf
 
chapter-14-sql-commands.pdf
chapter-14-sql-commands.pdfchapter-14-sql-commands.pdf
chapter-14-sql-commands.pdf
 
chapter-16-internet-and-open-source-concepts.pdf
chapter-16-internet-and-open-source-concepts.pdfchapter-16-internet-and-open-source-concepts.pdf
chapter-16-internet-and-open-source-concepts.pdf
 
chapter-17-web-designing2.pdf
chapter-17-web-designing2.pdfchapter-17-web-designing2.pdf
chapter-17-web-designing2.pdf
 

Recently uploaded

Chemical Tests; flame test, positive and negative ions test Edexcel Internati...
Chemical Tests; flame test, positive and negative ions test Edexcel Internati...Chemical Tests; flame test, positive and negative ions test Edexcel Internati...
Chemical Tests; flame test, positive and negative ions test Edexcel Internati...
ssuser79fe74
 
Pests of mustard_Identification_Management_Dr.UPR.pdf
Pests of mustard_Identification_Management_Dr.UPR.pdfPests of mustard_Identification_Management_Dr.UPR.pdf
Pests of mustard_Identification_Management_Dr.UPR.pdf
PirithiRaju
 
GUIDELINES ON SIMILAR BIOLOGICS Regulatory Requirements for Marketing Authori...
GUIDELINES ON SIMILAR BIOLOGICS Regulatory Requirements for Marketing Authori...GUIDELINES ON SIMILAR BIOLOGICS Regulatory Requirements for Marketing Authori...
GUIDELINES ON SIMILAR BIOLOGICS Regulatory Requirements for Marketing Authori...
Lokesh Kothari
 
Labelling Requirements and Label Claims for Dietary Supplements and Recommend...
Labelling Requirements and Label Claims for Dietary Supplements and Recommend...Labelling Requirements and Label Claims for Dietary Supplements and Recommend...
Labelling Requirements and Label Claims for Dietary Supplements and Recommend...
Lokesh Kothari
 
Pests of cotton_Sucking_Pests_Dr.UPR.pdf
Pests of cotton_Sucking_Pests_Dr.UPR.pdfPests of cotton_Sucking_Pests_Dr.UPR.pdf
Pests of cotton_Sucking_Pests_Dr.UPR.pdf
PirithiRaju
 
Seismic Method Estimate velocity from seismic data.pptx
Seismic Method Estimate velocity from seismic  data.pptxSeismic Method Estimate velocity from seismic  data.pptx
Seismic Method Estimate velocity from seismic data.pptx
AlMamun560346
 
Formation of low mass protostars and their circumstellar disks
Formation of low mass protostars and their circumstellar disksFormation of low mass protostars and their circumstellar disks
Formation of low mass protostars and their circumstellar disks
Sérgio Sacani
 
Biogenic Sulfur Gases as Biosignatures on Temperate Sub-Neptune Waterworlds
Biogenic Sulfur Gases as Biosignatures on Temperate Sub-Neptune WaterworldsBiogenic Sulfur Gases as Biosignatures on Temperate Sub-Neptune Waterworlds
Biogenic Sulfur Gases as Biosignatures on Temperate Sub-Neptune Waterworlds
Sérgio Sacani
 

Recently uploaded (20)

Chemical Tests; flame test, positive and negative ions test Edexcel Internati...
Chemical Tests; flame test, positive and negative ions test Edexcel Internati...Chemical Tests; flame test, positive and negative ions test Edexcel Internati...
Chemical Tests; flame test, positive and negative ions test Edexcel Internati...
 
Factory Acceptance Test( FAT).pptx .
Factory Acceptance Test( FAT).pptx       .Factory Acceptance Test( FAT).pptx       .
Factory Acceptance Test( FAT).pptx .
 
Pests of mustard_Identification_Management_Dr.UPR.pdf
Pests of mustard_Identification_Management_Dr.UPR.pdfPests of mustard_Identification_Management_Dr.UPR.pdf
Pests of mustard_Identification_Management_Dr.UPR.pdf
 
American Type Culture Collection (ATCC).pptx
American Type Culture Collection (ATCC).pptxAmerican Type Culture Collection (ATCC).pptx
American Type Culture Collection (ATCC).pptx
 
GUIDELINES ON SIMILAR BIOLOGICS Regulatory Requirements for Marketing Authori...
GUIDELINES ON SIMILAR BIOLOGICS Regulatory Requirements for Marketing Authori...GUIDELINES ON SIMILAR BIOLOGICS Regulatory Requirements for Marketing Authori...
GUIDELINES ON SIMILAR BIOLOGICS Regulatory Requirements for Marketing Authori...
 
Botany 4th semester file By Sumit Kumar yadav.pdf
Botany 4th semester file By Sumit Kumar yadav.pdfBotany 4th semester file By Sumit Kumar yadav.pdf
Botany 4th semester file By Sumit Kumar yadav.pdf
 
Labelling Requirements and Label Claims for Dietary Supplements and Recommend...
Labelling Requirements and Label Claims for Dietary Supplements and Recommend...Labelling Requirements and Label Claims for Dietary Supplements and Recommend...
Labelling Requirements and Label Claims for Dietary Supplements and Recommend...
 
GBSN - Microbiology (Unit 1)
GBSN - Microbiology (Unit 1)GBSN - Microbiology (Unit 1)
GBSN - Microbiology (Unit 1)
 
Pests of cotton_Sucking_Pests_Dr.UPR.pdf
Pests of cotton_Sucking_Pests_Dr.UPR.pdfPests of cotton_Sucking_Pests_Dr.UPR.pdf
Pests of cotton_Sucking_Pests_Dr.UPR.pdf
 
Seismic Method Estimate velocity from seismic data.pptx
Seismic Method Estimate velocity from seismic  data.pptxSeismic Method Estimate velocity from seismic  data.pptx
Seismic Method Estimate velocity from seismic data.pptx
 
SAMASTIPUR CALL GIRL 7857803690 LOW PRICE ESCORT SERVICE
SAMASTIPUR CALL GIRL 7857803690  LOW PRICE  ESCORT SERVICESAMASTIPUR CALL GIRL 7857803690  LOW PRICE  ESCORT SERVICE
SAMASTIPUR CALL GIRL 7857803690 LOW PRICE ESCORT SERVICE
 
Nightside clouds and disequilibrium chemistry on the hot Jupiter WASP-43b
Nightside clouds and disequilibrium chemistry on the hot Jupiter WASP-43bNightside clouds and disequilibrium chemistry on the hot Jupiter WASP-43b
Nightside clouds and disequilibrium chemistry on the hot Jupiter WASP-43b
 
TEST BANK For Radiologic Science for Technologists, 12th Edition by Stewart C...
TEST BANK For Radiologic Science for Technologists, 12th Edition by Stewart C...TEST BANK For Radiologic Science for Technologists, 12th Edition by Stewart C...
TEST BANK For Radiologic Science for Technologists, 12th Edition by Stewart C...
 
Vip profile Call Girls In Lonavala 9748763073 For Genuine Sex Service At Just...
Vip profile Call Girls In Lonavala 9748763073 For Genuine Sex Service At Just...Vip profile Call Girls In Lonavala 9748763073 For Genuine Sex Service At Just...
Vip profile Call Girls In Lonavala 9748763073 For Genuine Sex Service At Just...
 
9999266834 Call Girls In Noida Sector 22 (Delhi) Call Girl Service
9999266834 Call Girls In Noida Sector 22 (Delhi) Call Girl Service9999266834 Call Girls In Noida Sector 22 (Delhi) Call Girl Service
9999266834 Call Girls In Noida Sector 22 (Delhi) Call Girl Service
 
Formation of low mass protostars and their circumstellar disks
Formation of low mass protostars and their circumstellar disksFormation of low mass protostars and their circumstellar disks
Formation of low mass protostars and their circumstellar disks
 
Biogenic Sulfur Gases as Biosignatures on Temperate Sub-Neptune Waterworlds
Biogenic Sulfur Gases as Biosignatures on Temperate Sub-Neptune WaterworldsBiogenic Sulfur Gases as Biosignatures on Temperate Sub-Neptune Waterworlds
Biogenic Sulfur Gases as Biosignatures on Temperate Sub-Neptune Waterworlds
 
High Profile 🔝 8250077686 📞 Call Girls Service in GTB Nagar🍑
High Profile 🔝 8250077686 📞 Call Girls Service in GTB Nagar🍑High Profile 🔝 8250077686 📞 Call Girls Service in GTB Nagar🍑
High Profile 🔝 8250077686 📞 Call Girls Service in GTB Nagar🍑
 
Chemistry 4th semester series (krishna).pdf
Chemistry 4th semester series (krishna).pdfChemistry 4th semester series (krishna).pdf
Chemistry 4th semester series (krishna).pdf
 
Pulmonary drug delivery system M.pharm -2nd sem P'ceutics
Pulmonary drug delivery system M.pharm -2nd sem P'ceuticsPulmonary drug delivery system M.pharm -2nd sem P'ceutics
Pulmonary drug delivery system M.pharm -2nd sem P'ceutics
 

chapter-3-logic-gates.pdf

  • 1. Chapter 3- Logic Gates II PUC, MDRPUC, Hassan 1 | P a g e Chapter-3 LOGIC GATES  Introduction:  Gate: A Gate is a simply an electronic circuit which operates on one or more input signals and always produces an output signal.  Gates are digital (two state) circuits because the input and output signals are either low voltage (0) or high voltage (1).  Gates are often called logic circuits because they can be analyzed with Boolean algebra.  Gates are classified into two types:  Basic Gates:  NOT Gate:  A NOT gate has only one input and one output.  The output state is always the opposite of the input state.  A NOT Gate is also called as Inverter gate, because the output is not same as the input.  The output is sometimes called the complement (opposite) of the input.  The logical symbol and the truth table of NOT gate are given below. X X  OR Gate:  A OR gate has two or more input signal but only one output signal.  If any of the input signals is 1 (high), then the output is 1 (high).  The logical symbol for two-input OR gate and the truth table is given below. X 0 1 1 0 Logic gates Basic Gates Derived Gates AND OR NOR NAND XOR NOT XNOR
  • 2. Chapter 3- Logic Gates II PUC, MDRPUC, Hassan 2 | P a g e X F = X + Y Y  AND Gate:  A AND gate has two or more input signal but only one output signal.  When all the input signals are 1 (high), the output is 1 (high), otherwise the output is 0.  The logical symbol for two-input AND gate and the truth table is given below. X F = X .Y Y  NOR Gate:  A NOR gate has two or more input signal but only one output signal.  The NOR gate is a complemented of OR gate.  The output of NOR gate will be 1 only when all inputs are 0 and output will be 0 if any input represents a 1.  NOR is short form of NOT-OR.  The symbol is used to represent a NOR operation. So X + Y can be written as X NOR Y or X Y.  The logical structure shows an OR gate and NOT gate. For input X and Y, the output of the OR gate will be X+Y which is fed as input to the NOT gate. So the output of NOR gate is given by X + Y which is equal to X . Y X F = X + Y F = X + Y Y  The logical symbol for two-input NOR gate and the truth table is given below. X F = X + Y Y X Y F = X+Y 0 0 0 0 1 1 1 0 1 1 1 1 X Y F = X.Y 0 0 0 0 1 0 1 0 0 1 1 1 X Y Z F = + + 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 X Y F = + 0 0 1 0 1 0 1 0 0 1 1 0
  • 3. Chapter 3- Logic Gates II PUC, MDRPUC, Hassan 3 | P a g e  NAND Gate:  A NAND gate has two or more input signal but only one output signal.  The NAND gate is a complemented of AND gate.  The output of NAND gate will be 0 only when all inputs are 1 and output will be 0 if any input represents a 0.  NAND is short form of NOT-AND.  The symbol is used to represent a NOR operation. So X . Y can be written as X NAND Y or X Y.  The logical structure shows an AND gate and NOT gate. For input X and Y, the output of the OR gate will be X .Y which is fed as input to the NOT gate. So the output of NAND gate is given by X . Y which is equal to X + Y X F = X . Y F = X . Y Y  The logical symbol for two-input NAND gate and the truth table is given below. X F = X . Y Y  XOR (Exclusive-OR) Gate:  An exclusive-OR has two or more input signal but only one output signal.  Exclusive-OR gate is different form of OR gate.  Exclusive-OR gate produces output 1 for only those input combinations that have odd number of 1’s.  The output is 0 if there are even number of 1’s in the input.  The output is 1 if there are odd number of 1’s in the input.  In Boolean algebra, ϴ sign stands for XOR operation. Thus X XOR Y can be written as XϴY  If the output is given by: F = X ϴ Y X Y F = . 0 0 1 0 1 1 1 0 1 1 1 0 X Y Z F = . . 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0
  • 4. Chapter 3- Logic Gates II PUC, MDRPUC, Hassan 4 | P a g e F = X Y + X Y  The XOR gate has a symbol similar to OR gate, except the additional curved line of the input side. X F = X ϴ Y = X Y + X Y Y  The following truth table illustrates XOR operation for 2 and 3 inputs.  XNOR (Exclusive-NOR) Gate:  The XNOR gate is complement of XOR gate.  The output of XNOR is 1 only when the logic values of both X and Y is same i.e. either both are equal to 1 or both are 0.  Its output is 0 when its inputs are different.  In Boolean algebra, ʘ sign stands for XNOR operation. Thus X XNOR Y can be written as X ʘ Y  If the output is given by: F = X ʘ Y F = XY + XY  The XNOR gate has a symbol similar to NOR gate, except the additional curved line of the input side. X F = X ʘ Y = XY + X Y Y  The following truth table illustrates XOR operation for 2 and 3 inputs. Number Of 1’s Input Output X Y F = X ϴ Y EVEN 0 0 0 ODD 0 1 1 ODD 1 0 1 EVEN 1 1 0 Number of 1’s X Y Z F = X ϴ Y ϴ Z EVEN 0 0 0 0 ODD 0 0 1 1 ODD 0 1 0 1 EVEN 0 1 1 0 ODD 1 0 0 1 EVEN 1 0 1 0 EVEN 1 1 0 0 ODD 1 1 1 1 Number Of 1’s Input Output X Y F = X ʘ Y EVEN 0 0 1 ODD 0 1 0 ODD 1 0 0 EVEN 1 1 1 Number of 1’s X Y Z F = X ʘ Y ʘ Z EVEN 0 0 0 1 ODD 0 0 1 0 ODD 0 1 0 0 EVEN 0 1 1 1 ODD 1 0 0 0 EVEN 1 0 1 1 EVEN 1 1 0 1 ODD 1 1 1 0
  • 5. Chapter 3- Logic Gates II PUC, MDRPUC, Hassan 5 | P a g e  Universal Gate (NAND & NOR):  Universal gate is a gate using which all the basic gates can be designed.  NAND and NOR gate re called as Universal Gates, because all the Boolean functions can also be implemented using these two gates.  NAND and NOR gates are more popular as these are less expensive and easier to design.  Realization of all basic gates using NAND gate:  NAND to NOT:  In the figure we have two input NAND gate whose inputs are purposely connected together so that the same input is applied to both. F = X . X = X X  From the diagram X NAND X = X . X = X + X // DeMorgan’s 2nd Theorem = X X + X = X = Inverted Input = NOT gate  NAND to AND:  In the figure we have two NAND gates connected so that the AND operations is performed.  NAND gate 2 is used as a NOT gate. X F1 = X . Y F2 = X. Y = X.Y Y  From the diagram X NAND Y =F1= X . Y F2 = F1 . F1 = F1 + F1 // DeMorgan’s 2nd Theorem = X. Y X + X = X F2 = X.Y = AND gate  NAND to OR:  The OR operation can be implemented using NAND gates connected as shown in figure.  NAND gate 1 and NAND gate 2 are used as NOT to invert the inputs. F1 = X X F3 = X . Y = X + Y F2 = Y Y
  • 6. Chapter 3- Logic Gates II PUC, MDRPUC, Hassan 6 | P a g e  From the diagram X NAND Y F1 = X . X = X + X = X F2 = Y . Y = Y + Y = Y F3 = F1 . F2 = F1 + F2 // DeMorgan’s 2nd Theorem = X + Y X = X and Y = Y F3 = X +Y = OR gate  Realization of all basic gates using NOR gate:  NOR to NOT:  Figure shows that NOR gate with its inputs connected together behaves as a NOT gate. F = X + X = X X  From the diagram X NOR X = X + X = X . X // DeMorgan’s 1st Theorem = X X . X = X = Inverted Input = NOT gate  NOR to AND:  The AND operation can be implemented with NOR gate as shown in figure. Here NOR gate 1 and NOR gate 2 are used as NOT gate to invert inputs. F1 = X X F3= X + Y = X.Y F2 = Y Y  From the diagram X NOR Y F1 = X + X = X . X =X F2 = Y + Y = Y . Y =Y F3 = F1 + F2 = F1 . F2 // DeMorgan’s 1st Theorem = X . Y X = X and Y = Y F3 = X.Y = AND gate
  • 7. Chapter 3- Logic Gates II PUC, MDRPUC, Hassan 7 | P a g e  NAND to OR:  In the figure two NOR gates are arranged so that the OR operation is performed.  NOR gate 2 is used as NOT gate. X F1 = X + Y F2 = X + Y = X + Y Y  From the diagram X NOR Y F1 = X + Y F2 = F1 + F1 F2 = F1 . F1 // DeMorgan’s 1st Theorem = F1 = X + Y X = X F2 = X +Y = OR gate  Designing of Logic Circuit using all basic gates :  Designing of Logic Circuit using NAND and NOR gates: CHAPTER – LOGIC GATES BLUE PRINT VSA (1 marks) LA (3 Marks) - Total 01 Question 01 Question - 02 Questions Question No 1 Question No 20 - 04 Marks