Simulation of DVR by using Ultra Capacitor to Analysis of THD with and withou...
Low Power VLSI Design Presentation_final
1. Low Power VLSI Design
11/18/2015 1M.TECH_EC_VLSI_DESIGN
Guided by:
Dr. N.M Devashrayee
Prepared by:
Jitender Mor
14MECV06
2. Essentials for Developing Advance Low Power Design
Advance Low Power Techniques
Industry-Standard Low Power Language
Low Power Special Cells
Power-Conscious Methodologies
Low Power EDA Solution
3. Sources of Power Dissipation
Dynamic
Power
Switching
Power
Short Circuit
Power
Glitching
Power
Static Power
Diode
Leakage
R.B Leakage
B to B
Tunneling
Subthreshold
Leakage
Gate Leakage
Tunneling
Through Gate
Hot Carrier
Injection
Punch
Through
4. Pswitching = α CL Vdd
2 f
Psc = Vdd Imean = β/12 (Vdd – 2Vt)3 τ f
Pleakage = Vdd Ileakage
Factors of Power Dissipation
Supply Voltage
Physical Capacitance
Switching Activity
Threshold Voltage
6. Supply Voltage Scaling :
Static Voltage Scaling
• Device Feature Size Scaling
• Architectural Level Scaling
• Optimum Transistor Sizing
Multilevel Voltage Scaling
• Voltage Island
Dynamic Voltage & Frequency Scaling
Adaptive Voltage Scaling
7. Minimizing Switching Capacitance :
H/W S/W Tradeoff
Bus Encoding
• Gray Coding
• One Hot Coding
Clock Gating
Use of Number System
• 2’s compliment VS Sign Magnitude
8. Minimizing Leakage :
Variable VT CMOS
Multiple VT CMOS
Power Gating
Dual Subthreshold Supply
Fabrication of Multi Threshold Voltage :
Multiple Channel Doping
Multiple Oxide Thickness
Multiple Channel Length
Multiple Body Bias
9. Pdynamic α Vdd
2
Pdynamic decreases as Vdd reduces
But Delay also increases as Vdd reduces.
And we don’t want delay so we have to do something to
reduce Delay
10. To Reduce Delay
Scale Down VT with Vdd
Stand by Leakage will Increase
MTCMOS or VTCMOS to Reduce Leakage
Require Additional Processing Steps
Parallel Architecture
Require Additional
Hardware
11. Dual Subthreshold Supply
The Non-Critical path is made to operate at the reduced voltage VDDL, while the Critical path is
made to operate at the original voltage VDDH
Advantages :
1) no need for changing the regular fabrication process.
2) no need for creating parallel data paths causing painful area penalty.
The strategy of this approach consists of two steps:
1) finding the logic gates with excessive slack (difference between the required time and the
arrival time of a signal) in logic circuits and then
2) applying VDDL to those gates for slimming up the power
12. Need of Power Intent Language
HDL like Verilog, VHDL are functional intent language.
Don’t have Power Construct for describing things like Power
Shutdown, Isolation, State Retention.
Hence the need of new set of constructs, a new language
specially created to describe power behavior.
15. Low Power EDA Solution Tools
Synopsis Power Compiler
Advanced clock gating and low power
placement for lower dynamic power.
Calypto PowerPro CG
Reduces power by up to 60% with
little or no impact on timing or area.
16. Kyungseok Kim and Vishwani D. Agrawal Department of ECE, Auburn University, Auburn, AL 36849,
USA “Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level
Gates” in 12th Int'l Symposium on Quality Electronic Design 2011
Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa,Masahiro Kanazawa,
Makoto Ichida, and Kazutaka Nogami, Member, IEEE “Automated Low-Power Technique Exploiting
Multiple Supply Voltages Applied to a Media Processor” In IEEE JOURNAL OF SOLID-STATE CIRCUITS,
VOL. 33, No. 3, March 1998
K. Kim and V. D. Agrawal, “True Minimum Energy Design Using Dual Below-Threshold Supply
Voltages,” in Proceedings of 24th International Conference on VLSI Design, Jan. 2011
Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa, Masahiro Kanazawa,
Makoto Ichida, and Kazutaka Nogami, Member, IEEE “Automated Low-Power Technique Exploiting
Multiple Supply Voltages Applied to a Media Processor ” in IEEE JOURNAL OF SOLID-STATE CIRCUITS,
VOL. 33, NO. 3, MARCH 1998
http://nptel.ac.in/courses/106105034/
References
