The document provides a summary of Adya Jha's resume. It outlines their objective of seeking design and verification opportunities in semiconductor companies. It also lists their relevant coursework and projects completed, including cache design simulation, branch prediction simulation, and implementing cache coherence protocols. Their experience includes positions at AMD and Lantiq Communications where they worked on verification, directed and random testing, and boot from DRAM enhancements. Their education includes a B.E. in Electrical and Electronics Engineering from BITS Pilani with a 7.86 CGPA. Key skills include Verilog, C/C++, UVM, and tools like Modelsim and Cadence.

1. Adya Jha
+19193608987. ajha3@ncsu.edu. 512 Tartan Circle, Apartment 21, Raleigh 27606
Profile
Objective: Looking for Design and Verification opportunities across the X86, ARM, ASIC domains in leading semiconductor
companies. Actively looking for internship opportunities for summer 2016.
Currently seeking Masters in Computer Engineering at North Carolina State University. CGPA – 3.78/4
Relevant Coursework - Computer Design and Technology, Digital ASIC Design, Architecture of Parallel Computers.
Upcoming coursework – ASIC Verification, Embedded Systems Design, Advanced Computer Architecture.
Relevant Projects
 Cache and Memory Hierarchy Design. A simulator was coded to model L1, L2, victim caches. Programming language used - C.
 Dynamic Instruction Scheduling. A simulator was coded for out of order superscalar processor. Programming language used - C.
 Branch Prediction. A simulator was coded for Bimodal, Gshare and Hybrid branch predictors. Programming language used – C.
 Implementing MSI, MESI, Dragon coherence protocols. Programming language used – C++.
 Inclusive Cache structure with MESI protocol. Programming language used – C++.
 Hardware Accelerator for Bellman-Ford Algorithm. – A hardware accelerator was designed and coded in Verilog which takes a
source destination pair as inputs from input RAM, reads the graph from the Graph RAM, computes the shortest distance and
writes the results in the output RAM.
Experience
DESIGN ENGINEER 2, AMD, BANGALORE, INDIA — 2014-2015
 Verification Ownership - Sole verification ownership of features such as security memory regions (Trust zone and Exception Level
3 region) at IP level across projects. Responsibilities included test-planning, setting up the verification environment, generate
stimuli, random constrained tests and directed tests, partial functional coverage and signature debug. The verification
environment followed UVM standards.
DESIGN ENGINEER 1, AMD, BANGALORE, INDIA — 2012-2014.
Joined AMD as a part of the Unified North Bridge (UNB) team. Responsible for the following-
 Verification – Directed and Random tests were coded to verify various features. Random stimulus was driven as a part of
sequences on to the DUT and the functionalities were checked via checkers and scoreboards.
 Random configuration – Status Registers are randomly configured based on functionalities and constraints before simulations.
 Tester determinism – A virtual tester environment is created around the DUT and cycle by cycle accuracy is verified in comparison
with the RTL model.
 Boot From DRAM – It allows the device to fetch boot code from DRAM rather than I/O. The environment was enhanced from the
previous projects.
ACADEMY TRAINEE, LANTIQ COMMUNICATIONS, BANGALORE, INDIA — 2011-2012
 Understanding and verifying of generic modules at SOC level such as SPI, UART, DDR, JTAG, NAND Flash etc. Introduction to gate
level simulations for respective modules.
 Responsible for integration of multiple eVCs to calculate and analyze throughputs across different buses.
Education
BITS Pilani - B.E, Electrical and Electronics Engineering, MSc Chemistry - 2007 - 2012 CGPA – 7.86/10
Skills
Programming Languages - Verilog, C, C++, OpenMP
HDL – Verilog, Verification language – System Verilog
Verification Methodologies - UVM
Tools - Modelsim 6.4, Cadence NCSIM, Synopsys VCS.
Awards/Honours
Analysis of Traffic Flow Pattern using IR sensors, National Conference on Virtual and Intelligent Instrumentation, Pilani (2009)