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1
EE 548: Low Power VLSI Circuit Design, Spring 2018, Homework #1.
1. (25’) Figure 1 shows NMOS device with drain, source, and gate ports annotated. Determine the
mode of operation (saturation, triode or cutoff) and drain current ID for each of the biasing
configurations given below. Use the following transistor data in calculation:
NMOS: .2/3)/(,1.0,7.0,/60 12' LWVVVVAk Tn
a). .8.2,2.3 VVVV DSGS b). .2.2,8.3 VVVV DSGS
c). .6.1,6.0 VVVV DSGS
Figure 1. NMOS transistor Figure 2. MOSFET capacitance model
2. (25’) MOSFET capacitance model is given in Figure 2. The corresponding capacitances are
given by:
gbGBgdOgdGDgsOgsGS CCCCCCCC ;;
DdiffDBSdiffSB CCCC ;
The overlap capacitances: WxCCC doxgdOgsO
The channel capacitances Cgb, Cgs and Cgd can be looked up from the following table depending on
the operation region of the transistor.
Table 1. Average channel capacitances of MOS transistor for different operation regions
Operation Region Cgb Cgs Cgd
Cutoff CoxWLeff 0 0
Triode 0 CoxWLeff /2 CoxWLeff /2
Saturation 0 (2/3)CoxWLeff 0
Now consider an NMOS transistor with the following parameters:
Gate oxide thickness: nmtox 26 , Transistor size: mLmW 4.2,6.3
Lateral diffusion: .2.0 mxd
Dielectric constant of gate oxide: ./105.397.3 130 cmFox
Assume the transistor is in cutoff mode. Find out the values of ?,, GDGBGS CCC What is the total
gate capacitance seen from the gate? (Hint: GDGBGSg CCCC ).
3. (25’) 1). Take a CMOS inverter in Figure 3(a) as example,
i). If Vin=”0”, what’s the state (ON or OFF) of PMOS transistor Mp? What’s the state (ON or OFF)
of the NMOS transistor Mn?
ii). If Vin=”1”, what’s the state (ON or OFF) of PMOS transistor Mp? What’s the state (ON or OFF)
of the NMOS transistor Mn?
iii). At any moment in static state (Vin=”0” or “1” without change), are transistors Mp and Mn both
simultaneously ON? Is there any continuous conductive path between Vdd and Gnd? Is there any
static current flowing from Vdd to Gnd (ignoring leakage current)? Is there any power consumption
in static state (ignoring the leakage power)?
2). Now consider a pseudo-NMOS inverter in Figure 3(b). Briefly explain the worki.
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Content
· Corporate American Flag by Adbusters
· Women Should... Attached Files:
· Women Should.jpg (108.525 KB)
·
· Afghanistan - Tank Barrel Photograph by James
Nachtwey, 1996
· MLK vs. Charles Manson
· A poster from the ACLU.
· Words Kill Wars Attached Files:
· words kill wars.jpg (37.575 KB)
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· Mothers Eyes Attached Files:
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· Hendrix at Monterey Pop Festival, 1967
· The Original Playstation Attached Files:
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1
EE 548: Low Power VLSI Circuit Design, Spring 2018,
Homework #1.
1. (25’) Figure 1 shows NMOS device with drain, source, and
gate ports annotated. Determine the
mode of operation (saturation, triode or cutoff) and drain
2. current ID for each of the biasing
configurations given below. Use the following transistor data in
calculation:
b).
Figure 1. NMOS transistor Figure 2.
MOSFET capacitance model
2. (25’) MOSFET capacitance model is given in Figure 2. The
corresponding capacitances are
given by:
The channel capacitances Cgb, Cgs and Cgd can be looked up
from the following table depending on
the operation region of the transistor.
Table 1. Average channel capacitances of MOS transistor for
different operation regions
Operation Region Cgb Cgs Cgd
Cutoff CoxWLeff 0 0
Triode 0 CoxWLeff /2 CoxWLeff /2
Saturation 0 (2/3)CoxWLeff 0
Now consider an NMOS transistor with the following
3. parameters:
Dielectric constant of gate oxide: ./105.397.3 130 cmFox
Assume the transistor is in cutoff mode. Find out the values of
gate capacitance seen from the gate? (Hint: GDGBGSg CCCC
3. (25’) 1). Take a CMOS inverter in Figure 3(a) as example,
i). If Vin=”0”, what’s the state (ON or OFF) of PMOS transistor
Mp? What’s the state (ON or OFF)
of the NMOS transistor Mn?
ii). If Vin=”1”, what’s the state (ON or OFF) of PMOS
transistor Mp? What’s the state (ON or OFF)
of the NMOS transistor Mn?
iii). At any moment in static state (Vin=”0” or “1” without
change), are transistors Mp and Mn both
simultaneously ON? Is there any continuous conductive path
between Vdd and Gnd? Is there any
static current flowing from Vdd to Gnd (ignoring leakage
current)? Is there any power consumption
in static state (ignoring the leakage power)?
2). Now consider a pseudo-NMOS inverter in Figure 3(b).
Briefly explain the working principle of
the circuit.
2
i). If Vin=”0”, what’s the state (ON or OFF) of PMOS transistor
4. Mp? What’s the state (ON or OFF)
of the NMOS transistor Mn? Is there any static current flowing
from Vdd to Gnd (ignoring leakage
current)?
ii). If Vin=”1”, what’s the state (ON or OFF) of the NMOS
transistor Mn?
Are transistors Mp and Mn both simultaneously ON? Is there
any continuous conductive path
between Vdd and Gnd? Is there any static current flowing from
Vdd to Gnd (ignoring leakage current)?
Is there any power consumption in static state (ignoring the
leakage power)?
3). Compare the above CMOS and pseudo-NMOS inverters,
explain why CMOS technology
consumes less power than other VLSI technologies (pseudo-
NMOS, etc.).
(a). CMOS inverter
(b). pseudo-NMOS inverter
Figure 3. CMOS and pseudo-NMOS inverters
4.(25’) Implement the following logic function with Φn network
1). Plot the schematic of your circuit implementation.
2). Assume Vdd=5V, Gnd=0V, clock period TΦ=100ns. For the
given input pattern sequence ABC=111, 010,
101, 111, roughly sketch the output waveform of VY in Figure
4. When does the dynamic logic give the
correct output value?
3). Fill the table 2 for the values of output voltage VY for the
given input pattern sequence.
Due: 02/07/2018 (Wednesday) in class.
5. Figure 4. Voltage waveforms of dynamic (Φn network)
Table 2. Circuit output for given input pattern sequence
A B C Φ VY=? (“0” or “1”)
1 1 1 0
1 1 1 1
0 1 0 0
0 1 0 1
1 0 1 0
1 0 1 1
1 1 1 0
1 1 1 1
