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UIET CSJM UNIVERSITY MICROPROCESSOR (ECE-S304) B.TECH PAPER 2020-https://www.educationsmaterials.com/2020/12/uiet-csjm-university-microprocessor-ece.html
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COMMONWEALTH OF AUSTRALIACopyright Regulations 1969
COMMONWEALTH OF AUSTRALIA
Copyright Regulations 1969
Warning
This material has been reproduced and communicated to you by or on behalf of The Charles Darwin University pursuant to Part VB of the Copyright Act 1968 (the Act). The material in this communication may be subject to copyright under the Act. Any further reproduction or communication of this material by you may be the subject of copyright protection under the Act.
Do not remove this notice
(
Semester 2, 2016
FINAL EXAMINATION
DURATION
HIT274 – Network Engineering Applications
Teaching Period
Student Number
Given Names
Family Name
Reading
Time:
10
minutes
Writing
Time:
180
minutes
)
INSTRUCTIONS TO CANDIDATES
The examination has 3 sections
Section A:
Suggested Time:
Multiple Choice Questions: Answer ALL questions
45 minutes (30 marks)
Section B:
Suggested Time:
Short Answer Questions: Answer ALL questions
95 minutes (50 marks)
Section B:
Suggested Time:
Case Study: Answer ALL questions
40 minutes (20 marks)
Questions in section A must be answered directly onto the Examination Paper. Section B and C are to be answered in the booklets provided.
Note that questions ARE NOT of equal value.
EXAM CONDITIONS
You may begin writing from the commencement of the examination session.The reading time indicated above is provided as a guide only.
This is a CLOSED BOOK examination No calculators are permitted
No handwritten notes are permitted No dictionaries are permitted
ADDITIONAL AUTHORISED MATERIALS
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No additional printed material is permitted
1 x 16 Page Book 1 x Scrap Paper
(
THIS EXAMINATION PAPER AND SUPPLIED MATERIALS ARE NOT PERMITTED TO BE REMOVED FROM ANY EXAMINATION VENUE IN ANY CIRCUMSTANCE. THIS EXAMINATION IS PRINTED DOUBLE-SIDED.
)
Semester 2, 2016 FINAL EXAMINATION
HIT274 – Network Engineering Applications
Page 1 of 10
THIS EXAMINATION IS PRINTED DOUBLE-SIDED.
THIS PAGE HAS BEEN INTENTIONALLY LEFT BLANK.
Semester 2, 2016 FINAL EXAMINATION
HIT274 – Network Engineering Applications
Page 2 of 10
Section A Multiple Choice QuestionsTotal No of Marks for this section: 30
This section should be answered directly into this booklet by placing an X next to your chosen answers. Please ensure that your name and student number have been written on this booklet.
Each question is worth 1 mark.
Suggested Time allocation for Section A: 45 mins
Semester 2, 2016 FINAL EXAMINATION
HIT274 – Network Engineering Applications
Page 3 of 10
Section B
Short Answer QuestionsTotal No of Marks for this section: 50
This section should be answered in the Answer Booklet provided.
Marks for each question are indicated.
Suggested Time allocation for Section B: 95 mins
Question 1
Complete the table below:
Full IPv6
Abbreviated IPv6
a
FE80:0000:0000:0400:0000:0000:0000:054A
fe80:0:0:400::54a
b
4:b200:80:f0a:5000:c:885:a000
4:B200:80:F0A:5000:C:885:A000
c
0C0 ...
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The document discusses memory hierarchy and caching techniques. It begins by explaining the need for a memory hierarchy due to differing access times of memory technologies like SRAM, DRAM, and disk. It then covers concepts like cache hits, misses, block size, direct mapping, set associativity, compulsory misses, capacity misses, and conflict misses. Finally, it discusses using a second level cache to reduce memory access times by capturing misses from the first level cache.
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The document discusses memory hierarchy and caching techniques. It begins by explaining the need for a memory hierarchy due to differing access times of memory technologies like SRAM, DRAM, and disk. It then covers concepts like cache hits, misses, block size, direct mapping, set associativity, compulsory misses, capacity misses, and conflict misses. Finally, it discusses using a second-level cache to reduce memory access times by capturing misses from the first-level cache.
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Cache recap
The document discusses memory hierarchy and caching techniques. It begins by explaining the need for a memory hierarchy due to differing access times of memory technologies like SRAM, DRAM, and disk. It then covers topics like direct mapped caches, set associative caches, cache hits and misses, reducing miss penalties through multiple cache levels, and analyzing cache performance. Key goals in memory hierarchy design are reducing miss rates through techniques like larger blocks, higher associativity, and reducing miss penalties with lower level caches.
Cache recap
The document discusses memory hierarchy and cache performance. It introduces the concept of memory hierarchy to get the best of fast and large memories. It then discusses different memory technologies like SRAM, DRAM and disk and their access times. It explains the basic concepts of direct mapped cache, cache hits, misses and different ways to reduce miss penalties like using multiple cache levels. Finally, it classifies cache misses into compulsory, capacity and conflict misses and how these are affected based on cache parameters.
Cache recap
The document discusses memory hierarchy and cache performance. It introduces the concepts of memory hierarchy, cache hits, misses, and different types of cache organizations like direct mapped, set associative, and fully associative caches. It analyzes how cache performance is affected by miss rate, miss penalty, block size, cache size, and associativity. Adding a second level cache can help reduce the miss penalty and improve overall performance.
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Copyright Regulations 1969
Warning
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Semester 2, 2016
FINAL EXAMINATION
DURATION
HIT274 – Network Engineering Applications
Teaching Period
Student Number
Given Names
Family Name
Reading
Time:
10
minutes
Writing
Time:
180
minutes
)
INSTRUCTIONS TO CANDIDATES
The examination has 3 sections
Section A:
Suggested Time:
Multiple Choice Questions: Answer ALL questions
45 minutes (30 marks)
Section B:
Suggested Time:
Short Answer Questions: Answer ALL questions
95 minutes (50 marks)
Section B:
Suggested Time:
Case Study: Answer ALL questions
40 minutes (20 marks)
Questions in section A must be answered directly onto the Examination Paper. Section B and C are to be answered in the booklets provided.
Note that questions ARE NOT of equal value.
EXAM CONDITIONS
You may begin writing from the commencement of the examination session.The reading time indicated above is provided as a guide only.
This is a CLOSED BOOK examination No calculators are permitted
No handwritten notes are permitted No dictionaries are permitted
ADDITIONAL AUTHORISED MATERIALS
EXAMINATION MATERIALS TO BE SUPPLIED
No additional printed material is permitted
1 x 16 Page Book 1 x Scrap Paper
(
THIS EXAMINATION PAPER AND SUPPLIED MATERIALS ARE NOT PERMITTED TO BE REMOVED FROM ANY EXAMINATION VENUE IN ANY CIRCUMSTANCE. THIS EXAMINATION IS PRINTED DOUBLE-SIDED.
)
Semester 2, 2016 FINAL EXAMINATION
HIT274 – Network Engineering Applications
Page 1 of 10
THIS EXAMINATION IS PRINTED DOUBLE-SIDED.
THIS PAGE HAS BEEN INTENTIONALLY LEFT BLANK.
Semester 2, 2016 FINAL EXAMINATION
HIT274 – Network Engineering Applications
Page 2 of 10
Section A Multiple Choice QuestionsTotal No of Marks for this section: 30
This section should be answered directly into this booklet by placing an X next to your chosen answers. Please ensure that your name and student number have been written on this booklet.
Each question is worth 1 mark.
Suggested Time allocation for Section A: 45 mins
Semester 2, 2016 FINAL EXAMINATION
HIT274 – Network Engineering Applications
Page 3 of 10
Section B
Short Answer QuestionsTotal No of Marks for this section: 50
This section should be answered in the Answer Booklet provided.
Marks for each question are indicated.
Suggested Time allocation for Section B: 95 mins
Question 1
Complete the table below:
Full IPv6
Abbreviated IPv6
a
FE80:0000:0000:0400:0000:0000:0000:054A
fe80:0:0:400::54a
b
4:b200:80:f0a:5000:c:885:a000
4:B200:80:F0A:5000:C:885:A000
c
0C0 ...
Cache recap
The document discusses memory hierarchy and caching techniques. It begins by explaining the need for a memory hierarchy due to differing access times of memory technologies like SRAM, DRAM, and disk. It then covers concepts like cache hits, misses, block size, direct mapping, set associativity, compulsory misses, capacity misses, and conflict misses. Finally, it discusses using a second level cache to reduce memory access times by capturing misses from the first level cache.
Cache recap
The document discusses memory hierarchy and caching techniques. It begins by explaining the need for a memory hierarchy due to differing access times of memory technologies like SRAM, DRAM, and disk. It then covers concepts like cache hits, misses, block size, direct mapping, set associativity, compulsory misses, capacity misses, and conflict misses. Finally, it discusses using a second-level cache to reduce memory access times by capturing misses from the first-level cache.
Cache recap
The document discusses memory hierarchy and caching techniques. It begins by explaining the need for a memory hierarchy due to differing access times of memory technologies like SRAM, DRAM, and disk. It then covers concepts like cache hits, misses, block size, direct mapping, set associativity, compulsory misses, capacity misses, and conflict misses. It also discusses techniques for improving cache performance like multi-level caches, write buffers, increasing associativity, and interleaving memory banks.
Cache recap
The document discusses memory hierarchy and caching techniques. It begins by explaining the need for a memory hierarchy due to differing access times of memory technologies like SRAM, DRAM, and disk. It then covers topics like direct mapped caches, set associative caches, cache hits and misses, reducing miss penalties through multiple cache levels, and analyzing cache performance. Key goals in memory hierarchy design are reducing miss rates through techniques like larger blocks, higher associativity, and reducing miss penalties with lower level caches.
Cache recap
The document discusses memory hierarchy and cache performance. It introduces the concept of memory hierarchy to get the best of fast and large memories. It then discusses different memory technologies like SRAM, DRAM and disk and their access times. It explains the basic concepts of direct mapped cache, cache hits, misses and different ways to reduce miss penalties like using multiple cache levels. Finally, it classifies cache misses into compulsory, capacity and conflict misses and how these are affected based on cache parameters.
Cache recap
The document discusses memory hierarchy and cache performance. It introduces the concepts of memory hierarchy, cache hits, misses, and different types of cache organizations like direct mapped, set associative, and fully associative caches. It analyzes how cache performance is affected by miss rate, miss penalty, block size, cache size, and associativity. Adding a second level cache can help reduce the miss penalty and improve overall performance.
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- 1. Menu facebook twitter google+ Whatsapp Educations Materials DEPARTMENT OF ECE UIET CSJM UNIVERSITY MICROPROCESSOR (ECE-S304) SEMESTER:- 5th Mid Semester Examination-2020 Time: 1.5 Hrs MM : 20 Note: Attempt all the questions. A calculator is not allowed. Q1-If the memory chip size is 256 X1 bits, how many chips are required to make up 1KB of memory? Q2-The memory address of the last location of a 1KB memory chip is given as FBFF H Specify the memory map. Q3- Explain the process of Opcode-fetch. Q4- Calculate the execution time of the instruction LDA Address if the crystal frequency of an 8085 system is 3MHZ. Q5- Why Special purpose registers are 16 bits? Explain. Q6- Write an ALP to exchange the 24-bit data of memory locations 3000H onwards and 5000H onwards. Q7- Write an ALP to add two, 24-bit numbers present in registers B-D-H and L-C-E. Store 25-bit result in memory starting from 4000 H onwards using RIAM instruction. Q8- Write an ALP to perform the subtraction X - Y where X & Y are two, 8 bit BCD numbers present in memory from location 4000 H onwards and store the result in memory in sequence. DOWNLOAD IN PDF FORMAT UIET CSJM UNIVERSITY MICROPROCESSOR (ECE-S304) B.TECH PAPER 2020 Menu
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