The VLSI design flow involves several steps: (1) specifying the design requirements, (2) entering the design using schematics or a hardware description language, (3) performing functional simulation to verify the logic, (4) planning placement and routing of components on the chip, (5) conducting timing simulation to check timing performance, and (6) fabricating the chip using the generated masks.

1. VLSI DESIGN FLOW
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2. VLSI Design Flow
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4. Design Specification
The algorithm to be implemented with
mathematical representation.
1. Number of inputs and outputs in the design
and number of bits in each of them.
2. Number of bits used in the internal
arithmetic operation.
3. Number of clock signals to be used in the
design.
4. Maximum clock frequency to be used.
5. Area of chip.
6. Power dissipation of the chip.
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5. Design Entry
Design entry are of two types
Schematic Entry
Hardware description language(HDL)
Entry
In Schematic Entry circuit schematics are
drawn using GUI
The two dominant HDL are VHDL & VERILOG
Both language are used for describing digital
hardware
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6. Functional simulation
 For schematic & HDL design functional
simulation is performed before design
implementation to verify that the logic is correct
or not
 Schematic flow projects, functional simulation
is performed directly after completing design
entry tools
 HDL flow projects, functional simulation is
performed after the design has been entered &
synthesized
 The simulator displays input & output
waveforms
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7. Planning placement and
Routing
 This is the VLSI physical design or layout phase
 This is the process to determine the physical
location of device & make interconnection
between them.
 Partitioning is the task of dividing a ckt into sub
ckt
 Floorplanning is the step to determine the shape
of each sub ckt & pin locations
 Placement is determination of best position of
each module
 Routing is the method of interconnection of
different ckt components to minimize chip area &
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8. Timing simulation
Timing simulation is done with the clock
speed as per design specification
Timing analysis is done to see the
timing performance of a ckt i.e set up &
hold times of the flip-flop
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9. Fabrication into the chip
Once a chip design is complete it is
taped out for manufacturing
The masks are the geometric patterns
which are used for etching in
lithography in subsequent VLSI
fabrication
The output data of the design process
is send to foundry which manufactured
the chip using the mask
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