The document details the features and architecture of the 8085 microprocessor, highlighting its 8-bit data processing capabilities, clock operation, and memory address access. It describes the register structure, including general-purpose and special-purpose registers, along with the arithmetic logic unit (ALU) and instruction decoder. Additionally, the document covers the microprocessor's control circuitry and pin configuration related to power supply, data bus, and I/O operations.

1. UNIT 2:- MICROPROSSESOR 8085
Prof. Dravid d Parmar
Electrical Engineering Department
Dravid.parmar@ngivbt.edu.in
6353141147

2. • Features of 8085 :-
1. It is an 8-bit microprocessor i.e. it can accept, process, or provide 8-bit data
simultaneously.
2. It operates on a single + 5V power supply connected at Vcc power supply ground is
connected to V SS'
3. It operates on clock cycle with 50% duty cycle.
4. It has on chip clock generator. This internal clock generator requires tuned circuit like
LC, RC or crystal. The internal clock generator divides oscillator frequency by 2 and
generates clock signal, which can be used for synchronizing external devices. 5. It can
operate with a 3 MHz clock frequency. The 8085A-2 version can operate at the
maximum frequency of 5 MHz.

3. 6. It has 16 address lines, hence it can access (216) 64 kbytes of memory.
7. It provides 8-bit I/O addresses to access (28) 256 I/O ports.
8. In 8085, the lower 8-bit address bus (A0-A7) and data bus (Do-D7) are
multiplexed to reduce number of external pins. But due to this, external hardware
(latch) is required to separate address lines and data lines.

4. Architecture of 8085 :-

5.  Register Structure
•The shaded portion of this register model is called
programmer's model of 8085. It includes six 8-bit registers -
(B, C, D, E, H and L) one accumulator, one flag register and
two 16-bit registers (SP and PC). All these registers are
accessible to programmer and hence they are included in the
programmer's model.

6. Use of W and Z registers
The CALL instruction is used to transfer program control to a subprogram or subroutine.
This instruction pushes the current PC contents onto the stack and loads the given address
into the PC. The given address is temporarily stored in the W and Z registers and placed on
the bus for the fetch cycle. Thus the program control is transferred to the address given in
the instruction. XCHG instruction exchanges the contents of H with D and L with E. At the
time of exchange W and Z registers are used for temporary storage of data.

7. General purpose registers :
B, C, D, E, H and L are 8-bit general purpose registers can be used as a separate 8-bit
registers or as 16-bit register pairs BC, DE and HL. HL pair also functions as a data pointer
or memory pointer.
Special purpose registers :
a) Register A (Accumulator): It is a tri-state eight bit register. It is extensively used in
arithmetic, logic, load and store operations, as well as in, input/output (I/O) operations. Most
of the times the result of arithmetic and logical operations is stored in the register A. Hence it
is also identified as accumulator.

8. b) Flag Register (Program status word): MOST IMP GTU 4 TIMES REPEATED
It is an 8-bit register, in which five of the bits carry significant information in the form of flags: S (Sign
flag), Z (Zero flag), AC (Auxiliary Carry flag), P (Parity flag), and CY (Carry flag), as shown in Fig.
S-Sign flag: After the execution of arithmetic or logical operations, if bit D, of the result is 1, the sign flag
is set. In a given byte if D, is 1, the number will be viewed as negative number. If D, is 0, the number will
be considered as positive number.

9. Z-Zero flag: The zero flag sets if the result of operation in ALU is zero and flag resets if result is non
zero. The zero flag is also set if a certain register content becomes zero following an increment or
decrement operation of that register.
AC-Auxiliary Carry flag: This flag is set if there is an overflow out of bit 3 i.e., carry from lower
nibble to higher nibble (D3 bit to D4 bit). This flag is used for BCD operations and it is not available
for the programmer.
P-Parity flag: Parity is defined by the number of ones present in the accumulator. After an arithmetic
or logical operation if the result has an even number of ones, i.e. even parity, the flag is set. If the
parity is odd, flag is reset.
CY-Carry flag: This flag is set if there is an overflow out of bit 7. The carry flag also serves as a borrow
flag for subtraction. In both the examples shown below, the flag is set.

10. c) Instruction Register: In a typical processor operation, the processor first fetches the opcode of
instruction from memory (i.e. it places an address on the address bus and memory responds by placing
the data stored at the specified address on the data bus). The CPU stores this opcode in a register called
the instruction register. This opcode is further sent to the instruction decoder to select one of the 256
alternatives.
d) Program Counter (PC): The program counter is a special purpose register which, at a given time,
stores the address of the next instruction to be fetched. Since address of 8085 is 16-bit, the PC is 16-bit.
Program Counter acts as a pointer to the next instruction. How processor increments program counter
depends on the nature of the instruction; for one byte instruction it increments program counter by one,
for two byte instruction it increments program counter by two and for three byte instruction it increments
program counter by three such that program counter always points to the address of the next instruction.

11. e) Stack Pointer (SP): The stack is a reserved area of the memory in the RAM where temporary
information may be stored. A 16-bit stack pointer is used to hold the address of the most recent stack
entry.

12. Arithmetic Logic Unit (ALU)
The 8085's ALU performs arithmetic and logical functions on eight bit variables. The arithmetic unit
performs bitwise fundamental arithmetic operations such as addition and subtraction. The logic unit
performs logical operations such as complement, AND, OR and EX-OR, as well as rotate and clear. The
ALU also looks after the branching
Instruction Decoder and Machine Cycle Encoder
The instruction decoder decodes the opcode and accordingly gives information to thetiming and
control circuit. The 8085 executes seven different types of machine cycles. It gives the information
about which machine cycle is currently executing in the encoded form on the So, S, and IO/M lines.
This task is done by machine cycle encoder.

13.  Interrupt Control
The interrupt control block has five interrupt inputs RST 5.5, RST 6.5, RST 7.5, TRAP and INTR and
one acknowledge signal INTA. It controls the interrupt activity of 8085 microprocessor.
 Serial I/O Control
The 8085's serial I/O control provides two lines, SOD and SID for serial communication. The Serial
Output Data (SOD) line is used to send data serially and Serial Input Data (SID) line is used to receive
data serially.
 Timing and Control Circuitry
The control circuitry in the processor 8085 is responsible for all the operations. The control circuitry and
hence the operations in 8085 are synchronized with the help of clock signal. Along with the control of
fetching and decoding operations and generating appropriate signals for instruction execution, control
circuitry also generates signals required to interface external devices to the processor, 8085.

14. 8085 Pin Diagram :-
a) Power supply and frequency signals.
b) Data bus and address bus
c) Control and status signal
e) Serial I/O signals
g) Reset signals
d) Interrupt signals
f) DMA signals

15. A).Power Supply and Frequency Signals
i) Vcc : It requires a single + 5 V power supply.
ii) Vss: Ground reference.
iii) X, and X2 (Input): A +tuned circuit like LC, RC or crystal is connected at these two pins. The
internal clock generator divides oscillator frequency by 2, therefore, to operate a system at 3 MHz, the
crystal of tuned circuit must have a frequency of 6 MHz
iv) CLK OUT (Output): This signal is used as a system clock for other devices. Its frequency is half the
oscillator frequency.

16. b) Data bus and address bus
A) AD0, to AD7, (Input/Output): The 8-bit data bus (Do - D7) is multiplexed with the lower half (Ao
– A7) of the 16-bit address bus. During first part of the machine cycle (T1), lower 8 bits of memory
address or I/O address appear on the bus. During remaining part of the machine cycle (T2 and T3)
these lines are used as a bi-directional data bus.
B) A8 to A15 (Output) : The upper half of the 16-bit address appears on the address lines A8 to A 15.
These lines are exclusively used for the most significant 8 bits of the 16-bit 8 address lines.

17. A) ALE (Address Latch Enable) (Output): We know that ADo to AD7, lines are multiplexed and the
lower half of address (Ao - A7) is available only during T1 of the machine cycle. This lower half of
address is also necessary during T2 and T3 of machine cycle to access specific location in memory or I/O
port. This means that the lower half of an address must be latched in T1 of the machine cycle, so that it is
available throughout the machine cycle. The latching of lower half of an address bus is done by using
external latch and ALE signal from 8085.
B) RD and WR (Output): A low on RD indicates that the data must be read from the selected memory
location or I/O port via data bus. A low on WR indicates that the data must be written into the selected
memory location or I/O port via data bus.
c) Control And status signal

18. C) IO / M, So and S1 (Output) : IO/M indicates whether I/O operation or memory operation is being
carried out. S1 and So indicate the type of machine cycle in progress.
D) READY (Input): It is used by the microprocessor to sense whether a peripheral is ready or not for
data transfer. If not, the processor waits. It is thus used to synchronize slower peripherals to the
microprocessor.

19. e) Serial I/O signals:
A) SID (Serial I/P Data) (Input): This input signal is used to accept serial data bit by bit from the
external device.
B) SOD (Serial O/P Data) (Output): This is an output signal which enables the transmission of
serial data bit by bit to the external device.

20. A) RESET IN (Input): A low on this pin
1) Sets the program counter to zero (0000H) and clears the INTE flag.
2) Resets the interrupt enable and HLDA flip-flops.
3) Tri-states the data bus, address bus and control bus.
(Note: Only during RESET is active).
4) Affects the contents of processor's internal registers randomly.
B) RESET OUT (Output): This active high signal indicates that processor is being reset. This signal is
synchronized to the processor clock and it can be used to reset other devices connected in the system.
g) Reset signals :-

21. Serial I/O Signals
A) SID (Serial I/P Data) (Input): This input signal is used to accept serial data bit by bit from the
external device.
B) SOD (Serial O/P Data) (Output): This is an output signal which enables the transmission of serial
data bit by bit to the external device.
DMA Signal
A) HOLD (Input): This signal indicates that another master is requesting for the use of address bus,
data bus and control bus.
B) HLDA (Output): This active high signal is used to acknowledge HOLD request.

22. Demultiplexing AD7-AD0
• With help of diagram show how to de multiplexing of addressdata bus AD0-AD7
can be archived (IMP)

23. •The latching of lower half of an address is done by using external latch and ALE signal from 8085.
The Fig shows the hardware connection for latching the lower half of an address. The IC 74LS373 is
an 8-bit latch, having 8 D flip-flops.
•The input is transferred to the output only when clock is high.
•This clock signal is driven by ALE signal from 8085. The ALE signal is activated only during T1, so
input is transferred to the output only during T1 i.e. address (Ao - A7) on the AD to AD, multiplexed
bus.
•In the remaining part of the machine cycle, ALE signal is disabled so output of the latch (Ao - A7)
remains unchanged. To latch lower half of an address, in each machine cycle, the 8085 gives ALE
signal high during T1 of every machine cycle. With this circuit, we can use output of latch as lower half
address bus and input of latch (AD♂-AD1) as data