Atomic Rules UDP Offload Engine (UOE) is an FPGA IP core that inter-converts Ethernet L2 Frames to/from IP L4 Datagrams.

1. UDP Offload Engine
(UOE)
Shep Siegel, CTO
Atomic Rules LLC
1©2020 Atomic Rules LLC
Shepard.Siegel@atomicrules.com
UDP Offload Engine (UOE)
2020-01-14

2. UDP Offload Engine (UOE)
• UDP “in hardware”
– Line-Rate Conversion of L2-Frames↔L4-Datagrams
– Near-Theoretical Throughput and Latency
– Industry-Standard AXI Hardware Interfaces
– Industry-Standard RFC Compliance
– Supports Multiple Line-Rates
• (-8B) 8 Byte Datapath – Up to 25 GbE (1/10/25)
• (-64B) 64 Byte Datapath – Up to 100 GbE (1/20/25/40/50/100)
– Interfaces with Popular FPGA MACs
• Note: PHY and MAC IP is not part of UOE
• Stable, Mature and Field-Proven Product
– First GA release in CY2015 – Lot’s of “miles” on this code
– Xilinx Vivado 2019.2 support today in UOE Release 2019.11
2©2020 Atomic Rules LLC

3. UOE: Why?
• RTL Circuit maintains high-line rate
– Deterministic behavior, No software latency-jitter
• Simplicity and Reliability of an RTL digital circuit
– Single Clock Domain
• UDP interoperates with switches and NICs
– Routable L4 UDP/IP avoids pitfalls of L2 “flat-earth”
– 16 Multicast Groups supported (IGMPv2 RFC-2236)
• Modest FPGA Area
– ~20K LUT/DFF and ~50 BRAM (8 Byte Datapath)
– ~85K LUT/DFF and ~60 BRAM (64 Byte Datapath)
– Can have as many UOE cores per FPGA as required
3©2020 Atomic Rules LLC

4. UOE: How?
• Two different datapath widths available to
best match your application’s line rate needs
– Up to 25 GbE – 8 Byte (64b) Data Path (-8B)
• for 10 GbE typical core clock: 156.25 MHz
• for 25 GbE typical core clock : 390.625 MHz
– Up to 100 GbE – 64 Byte (512b) Data Path (-64B)
• for 100 GbE typical core clock : 250 MHz
• for 50 GbE typical core clock : 125 MHz
• for 40 GbE typical core clock : 100 MHz
4©2020 Atomic Rules LLC

5. High-Level Block Diagram
5©2020 Atomic Rules LLC
Red/Blue Datapaths are either
8Byte (64b) or 64Byte (512b) wide

6. Design Flows Supported
• IEEE Verilog Top-Level
• IEEE SystemVerilog
• IEEE VHDL (wrapper)
• Vivado IP Integrator (IPI) (Next two slides)
• Un-Encrypted Verilog Netlist (for Simulation)
6©2020 Atomic Rules LLC

7. Vivado IPI 1/2
7©2020 Atomic Rules LLC

8. Vivado IPI 2/2
8©2020 Atomic Rules LLC

9. 100 GbE UDP Offload
9©2020 Atomic Rules LLC

10. > 100 Gbps Throughput
10©2020 Atomic Rules LLC
L2 MTU: 1550 Bytes

11. Demo UOE Today!
shep@ar-4770k:~$ tclsh main.tcl 40878
reset load_config config run watch stop uoedump
pktgen is not running and is not paused. No need to reset.
Packets MBytes MBits (persecond)
3591722 14039 112312
3595155 14043 112344
…
3594307 14039 112312
3593991 14040 112320
pktchk stopped.
UOE Stats............
r_Total = 215754260
r_ARP = 2
r_UDP = 215754258
s_dgReceived = 71918086
s_dgSent = 71918086
r_dgReceived = 71918086
r_dgSent = 71918086
r_fragsDecoded = 143836172
11©2020 Atomic Rules LLC
About 112 Gbps sustained
without 100 GbE MAC line rate
constraint.
64B core clocked at 250 MHz

12. Royalty-Free License
• Royalty-Free
– No per-unit accounting friction
• Named-Project and Site Licenses available
– 8 Byte Datapath (up to and including 25 GbE)
• Named-Project $20K USD (AR-UOE-8B-NP)
– 64 Byte Datapath (up to and including 100 GbE)
• Named-Project $30K USD (AR-UOE-64B-NP)
– Incudes 1 Year support and quarterly updates
12©2020 Atomic Rules LLC

13. Thank You!
13©2020 Atomic Rules LLC

14. Backup Material
14©2020 Atomic Rules LLC

15. Core Beliefs and Axioms
15©2020 Atomic Rules LLC
• Our Customer’s Success is Key
• Separation of Concerns
• Divide and Conquer
• Automate or Die
• Write Things Once
• Interface Before Implementation
• Functional Correctness First
• Performance Correctness Improved Iteratively
• Components Must Compose
• Components Must Work as Expected
• IP Should be Portable, Vendor-Agnostic if possible

16. Partner Roster
16©2020 Atomic Rules LLC
• 25G / 50G Ethernet Consortium
• 25-50-100 Ethernet Alliance
• Accellera/OCP-IP Community Member
• Amazon F1 Instance Partner
• ARM Connected Community Member
• BittWare Solution Partner
• Bluespec Technology Partner
• DPDK Project Corporate Member
• FPGA, FCCM and FPL ‘F’ Conference Sponsors
• Intel Network Builders
• Linux Foundation Corporate Member
• MathWorks Connections Partner
• NetFPGA Infrastructure Developer
• OpenCPI Infrastructure Developer
• P4 Language Consortium Member
• PCI-SIG Corporate Member
• VITA Trade Association Member
• Xilinx Alliance Member Partner