1. 10530 Garvey Ave, EL Monte, CA 91733
Mobile: (305)799-6882
E-mail: tianyi0001@gmail.com
Background Highlights
• 6 years research, development and design experiences in real-time systems, embedded system design, and process
variation-/thermal-/power-aware computing.
• 3 years solid project experiences in FPGA design.
• Strong programming experiences and skills in C/C++/Matlab (6 years), and Verilog HDL (3 years).
• A quick learner with critical thinking; excellent writing and verbal communication skills.
Skills
• Programming/Tools:
- C/C++, Matlab, Verilog HDL, Python, HTML, Simics/GEMS/GEM5, Xilinx ISE/EDK, NI myDAQ, PSPICE,
SimpleScalar.
• IDE/Platform:
- Visual Studio, Xcode, NI Multisim, Windows, Linux, iOS.
Education
• Ph.D in Electrical and Computer Engineering - Florida International University, 2015, GPA 3.86/4.0
• M.E. in Integrated Circuit Design - Beihang University, Beijing, 2009, GPA 3.9/4.0
• B.E. in Software Engineering - Beihang University, Beijing, 2006, GPA 3.4/4.0
Experience
• 2012.01-2015.07 Research Assistant, Advanced Real-time and Computing Systems Lab (ARCS),
Florida International University
- Statistical Real-Time Scheduling on Multiprocessor Platforms:
• Defined
new
harmonic
relationship
for
tasks
with
statistical
execution
times.
• Proposed
task
allocation
algorithms
to
schedule
tasks
on
multiprocessor
platforms.
• Guaranteed
the
deadline
miss
probability
for
each
task
while
minimized
the
number
of
processors
used.
- Process-Variation-Aware Embedded System Design:
• Analyzed
the
performance
deviation
of
applications
under
process
variation.
• Developed
a
novel
metric
based
on
opportunity
cost.
• Proposed
topology
virtualization
framework
to
re-­‐map
applications
(DAGs)
for
performance
maximization.
- Thermal-Aware Embedded System Design:
• Proposed
a
fast
calculation
for
steady-­‐state
temperature
on
multiprocessor
platforms.
• Built
interdependent
relationship
between
leakage
variation
and
temperature
to
obtain
accurate
steady-­‐state
peak
temperature.
• Developed
novel
heuristics
to
swap
workloads
between
cores
to
minimize
the
peak
temperature
on
multiprocessor
platforms.
• 2009.08-2011.12 Teaching Assistant, Florida International University
- Teaching Assistant for systems lab, logic design lab, electronics lab, and embedded systems lab: In
Tianyi Wang

2. charge of lab manual designing, projects and exams.
• 2007.09-2009.06 Master Student, Beihang University (China)
- Hardware Acceleration on FPGA platform: Implementation of an Intellectual Property (IP) in the form of
Hardware acceleration for AES (Advanced Encryption Standard) algorithm.
- PicoBlaze: Built a complete system using PicoBlaze soft-core embedded in FPGA including VGA display,
buzzer, and counter controls through the buttons on the FPGA.
Honors & Awards .
• Graduate Research Assistantship, Advanced Real-time and Computing Systems Lab, FIU, 2012-2014
• Graduate Teaching Assistantship, Department of Electrical and Computing Engineering, FIU 2009-2011
• Outstanding Graduate Student Award, Beihang University, 06/2009 (10/320)
• Freshmen Training Pacemaker, Beihang University, 06/2003
• Director of Student TV, Beihang University, 08/2002 - 12/2003
Publications
• Tianyi
Wang,
Gang
Quan,
Shangping
Ren
and
Meikang
Qiu.
"Topology
Virtualization
for
Throughput
Maximization
on
Many-­‐Core
Platforms", Parallel
and
Distributed
Systems
(ICPADS),
2012
IEEE
18
th
International
Conference
on,
vol.,
no.,
pp.408,
415,
17-­‐19
Dec.
2012.
(87/294
=
29.6%)
• Tianyi
Wang,
Ming
Fan,
Gang
Quan
and
Shangping
Ren.
"Heterogeneity
Exploration
for
Peak
Temperature
Reduction
on
Multi-­‐Core
Platforms",
Quality
Electronic
Design
(ISQED),
2014
15
th
International
Symposium
on.
• Tianyi
Wang,
Linwei
Niu,
Shaolei
Ren
and
Gang
Quan.
“Multi-­‐Core
Fixed-­‐Priority
Scheduling
of
Real-­‐Time
Tasks
with
Statistical
Deadline
Guarantee”,
Design,
Automation
Test
in
Europe
Conference
Exhibition
(DATE),
2015.
(205/915
=
22.4%)
• Tianyi
Wang,
Qiushi
Han,
Shaolei
Ren,
Shangping
Ren,
Meikang
Qiu
and
Gang
Quan.
“On
harmonic
fixed-­‐priority
periodic
real-­‐time
tasks
with
explicit
deadlines”,
in
Real-­‐Time
System
Symposium
(RTSS),
2015
IEEE
36
th
.
(Submitted)
• Qiushi
Han,
Tianyi
Wang
and
Gang
Quan.
"Enhanced
Fault-­‐Tolerant
Fixed-­‐Priority
Scheduling
of
Hard
Real-­‐Time
Tasks
on
Multi-­‐Core
Platforms",
Embedded
and
Real-­‐Time
Computing
Systems
and
Applications
(RTCSA).
(Accepted)
• Xiaokun
Yang,
Tianyi
Wang
and
Jean
Andrian,
"A
High
Efficiency
Bus
Transfer
Mode
for
AES-­‐Encrypted
Embedded
Systems,"
Quality
Electronic
Design
(ISQED),
2016
17
th
International
Symposium
on.
(Submitted)
• Xiaokun
Yang,
Tianyi
Wang
and
Jean
Andrian,
"A
Solution
of
MSBUS
Integration
from
Multiple
IP
Vendors",
Quality
Electronic
Design
(ISQED),
2016
17
th
International
Symposium
on.
(Submitted)