SPARC (Scalable Processor Architecture), developed by the SPARC Consortium and adopted by Sun Microsystems in 1985, is a CPU instruction set architecture based on RISC designs. It features an integer unit, floating-point unit, and optional coprocessor, supporting advanced multitasking through threads and register window techniques for efficient function calls. The architecture includes various instruction categories and is designed for high performance with concurrent processing capabilities.

2. *SPARC stands for Scalable Processor ARChitecture.
*SPARC, formulated by SPARC Consortium and
adopted by Sun Microsystems in 1985, is based on
the RISC I & II designs engineered at the University
of California at Berkeley from 1980 through 1982.
*SPARC is a CPU instruction set architecture (ISA),
derived from a Reduced Instruction Set
Architecture (RISC).

3. *THE SPARC PROCESSOR
*The Modules
*Integer Unit (IU)
*Floating Point Unit (FPU)
*Co-Processor
*Instructions
*The Register Window Concept
*Traps
*Pipelining

4. *The SPARC processor is divided into three parts:
*an Integer Unit (IU)
*a Floating-Point Unit (FPU)
*an optional Coprocessor (CP), each with its own
registers. (32-bits wide).
*The SPARC processor can be in either of 2 modes:
*Supervisor mode: The processor can execute any
instruction, including the privileged instructions.
*User mode: “User Application” programs will be
executed in user mode.

5. Integer Unit
(IU)
Floating-Point
Unit
(FPU)
CoProcessor
(CP)

6. *Contains the general purpose registers and controls the
overall operation of the processor.
*Executes the integer arithmetic instructions and computes
memory addresses for loads and stores.
*Maintains the program counters and controls instruction
execution for the FPU and the CP.
*May contain from 40 to 520, 32-bit general-purpose registers
which corresponds to a group of 8 global registers and a
circular stack of 16 registers, known as register windows.

7. *The FPU has thirty-two 32-bit-wide
registers.
*Double-precision values occupy an even-
odd pair and extended-precision values
occupy an aligned group of four registers.
*The FPU’s registers are accessed
externally only via load and store
instructions; there is no direct path
between the IU and the FPU.

8. *Coprocessor, additional processor used in some computers
to perform specialized tasks such as extensive arithmetic
calculations(floating-point arithmetic),graphics, signal
processing, string processing, cryptography or I/O
interfacing with peripheral devices
*The coprocessor instructions mirror the floating-point
instructions ;
*Load/store coprocessor,
*Branch on coprocessor condition codes,
*Coprocessor operate (CPop).
*Coprocessor operate instructions can execute concurrently
with integer instructions.
*The coprocessor unit has its own set of 32-bit registers.

9. *Instructions fall into six basic categories
*Load/Store
*Arithmetic/Logical/Shift
*Control Transfer
*Read/Write Control Register
*Floating-point Operate
*Coprocessor Operate

11. * Register windows are implemented to improve the performance of a
processor by reducing the number of stack operations required for function
calls and returns.
*
The active window is identified by the 5-bit Current Window Pointer
(instruction pointer)(CWP).
* Decrementing the CWP at procedure entry causes the next window to
become active.
* Incrementing the CWP at procedure entry causes the previous window to
become active.
* Register window overflow and underflow conditions are handled in
software by a kernel trap handler.
* The Window Invalid Mask (WIM) can tag any window so that an overflow or
underflow trap is generated whenever the CWP is about to point a tagged
window.

12. *The additional registers are
hidden from view until you
call a subroutine or other
function. Where other
processors would push
parameters on a stack for
the called routine to pop
off, SPARC processors just
"rotate" the register window
to give the called routine a
fresh set of registers.
*The old window and the
new window overlap, so
that some registers are
shared.

13. *A trap is an unexpected procedural call.
*Traps
*decrement the CWP to the next register window.
*cause the hardware to write the trapped program
counters and state of the registers into the local
registers of the new window.

15. •Threads have become a vital part of the computing as they allow the
processor to perform multiple tasks at the same time making the tasks
faster.
•And also making the computer capable of multitasking.
• Due to threads only you are able to browse the web as well as listen to
music simultaneously.
•4 threads (group) supported per pipeline.
•Each thread has unique
1. Register state.
2. Instruction buffers.
3.Store buffers.
•The thread group shares:
1. L1 caches.
2. TLBs.
3. Execution units.
4. Pipeline resources
SPARC Pipeline

18. *

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