SPICE MODEL of TC7PA175FU in SPICE PARK
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SPICE MODEL of TC7PA175FU in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
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SPICE MODEL of TC7PA175FU in SPICE PARK
- 1. Device Modeling Report COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT PART NUMBER : TC7PA175FU MANUFACTURER : TOSHIBA Bee Technologies Inc. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 2. Truth Table Circuit simulation result U1:CLR 0 U1:D 1 5.0V SEL>> 0V V(U1:CK) 4.0V 2.0V 0V 1.5us 2.0us 2.5us 3.0us V(U1:Q) Time Evaluation circuit OFFTIME = .5uSDSTM1 U1 ___ ONTIME = .5uS CLK CK CLR LO DELAY = 0.5u STARTVAL = 0 CK ___ OPPVAL = 1 GND CLR VCC D Q HI D Q TC7PA175 V1 R1 3.6 1MEG 0 Comparison table Input OUTPUT Q %Error CLR D CK Measurement Simulation L X X L L 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 3. Truth Table Circuit simulation result U1:CLR U1:D 5.0V SEL>> 0V V(U1:CK) 4.0V 2.0V 0V 1.0us 1.5us 2.0us 2.5us 3.0us V(U1:Q) Time Evaluation circuit OFFTIME = .5uSDSTM1 U1 ___ ONTIME = .5uS CLK CK CLR HI DELAY = 0.5u STARTVAL = 0 CK ___ OPPVAL = 1 GND CLR VCC D Q LO D Q TC7PA175 V1 R1 3.6 1MEG 0 Comparison table Input OUTPUT Q %Error CLR D CK Measurement Simulation H L L L 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 4. Truth Table Circuit simulation result U1:CLR 1 U1:D 1 5.0V SEL>> 0V V(U1:CK) 4.0V 2.0V 0V 1.0us 1.5us 2.0us 2.5us 3.0us V(U1:Q) Time Evaluation circuit OFFTIME = .5uSDSTM1 U1 ___ ONTIME = .5uS CLK CK CLR HI DELAY = 0.5u STARTVAL = 0 CK ___ OPPVAL = 1 GND CLR VCC D Q HI D Q TC7PA175 V1 R1 3.6 1MEG 0 Comparison table Input OUTPUT Q %Error CLR D CK Measurement Simulation H H H H 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 5. Truth Table Circuit simulation result U1:CLR 1 U1:D 1 5.0V SEL>> 0V V(U1:CK) 4.0V 2.0V 0V 1.5us 2.0us 2.5us 3.0us V(U1:Q) Time Evaluation circuit OFFTIME = .5uSDSTM1 U1 ___ ONTIME = .5uS CLK CK CLR HI DELAY = 0.5u STARTVAL = 0 CK ___ OPPVAL = 1 GND CLR VCC D Q HI D Q TC7PA175 V1 R1 3.6 1MEG 0 Comparison table Input OUTPUT Q %Error CLR D CK Measurement Simulation H X Qn Qn 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 6. High Level Input Voltage (2.7 V < VCC ≤ 3.6 V) Circuit simulation result 3.0V 2.0V Output 1.0V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q1) Time Evaluation circuit CLK1 U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D1 Q1 V31 TC7PA175 V1 = 0 V21 V2 = 3.3 TD = 3n V22 TR = 2.5n 2 3.3 TF = 2.5n R1 PW = 2.5n PER = 10n 1G 0 Comparison table VCC = 3.3 V Measurement Simulation %Error VIH (V) 2 2 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 7. Low Level Input Voltage (2.7 V < VCC ≤ 3.6 V) Circuit simulation result 3.0V 2.0V Output 1.0V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q1) Time Evaluation circuit CLK1 U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D1 Q1 V31 TC7PA175 V1 = 0 V2 = 3.3 V21 TD = 3n V22 TR = 2.5n 0.8 TF = 2.5n R1 3.3 PW = 2.5n PER = 10n 1G 0 Comparison table VCC = 3.3 V Measurement Simulation %Error VIL (V) 0.8 0.8 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 8. High Level Input Voltage (2.3 V ≤ VCC ≤ 2.7 V) Circuit simulation result 2.0V Output 1.0V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q1) Time Evaluation circuit CLK1 U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D1 Q1 V31 TC7PA175 V1 = 0 V2 = 2.5 V21 TD = 3n V22 TR = 2.5n 1.6 TF = 2.5n R1 2.5 PW = 2.5n PER = 10n 1G 0 Comparison table VCC = 2.5 V Measurement Simulation %Error VIH (V) 1.6 1.6 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 9. Low Level Input Voltage (2.3 V ≤ VCC ≤ 2.7 V) Circuit simulation result 2.0V Output 1.0V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q1) Time Evaluation circuit CLK1 U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D1 Q1 V31 TC7PA175 V1 = 0 V2 = 2.5 V21 TD = 3n V22 TR = 2.5n 0.7 TF = 2.5n R1 2.5 PW = 2.5n PER = 10n 1G 0 Comparison table VCC = 2.5 V Measurement Simulation %Error VIL (V) 0.7 0.7 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 10. High Level Input Voltage (1.65 V ≤ VCC < 2.3 V) Circuit simulation result 1.5V 1.0V Output 0.5V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q1) Time Evaluation circuit CLK1 U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D1 Q1 V31 TC7PA175 V1 = 0 V2 = 1.8 V21 TD = 3n V22 TR = 2.5n 1.26 TF = 2.5n R1 1.8 PW = 2.5n PER = 10n 1G 0 Comparison table VCC = 1.8 V Measurement Simulation %Error Min VIH = (VCC*0.7) (V) 1.26 1.26 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 11. Low Level Input Voltage (1.65 V ≤ VCC < 2.3 V) Circuit simulation result 1.5V 1.0V Output 0.5V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q1) Time Evaluation circuit CLK1 U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D1 Q1 V31 TC7PA175 V1 = 0 V2 = 1.8 V21 TD = 3n V22 TR = 2.5n 0.36 TF = 2.5n R1 1.8 PW = 2.5n PER = 10n 1G 0 Comparison table VCC = 1.8 V Measurement Simulation %Error Max VIL = (VCC*0.2) (V) 0.36 0.36 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 12. High Level Output Voltage (2.7 V < VCC ≤ 3.6 V) Circuit simulation result 3.0V 2.0V Output 1.0V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q) Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V1 TC7PA175 V1 = 0 V3 V2 = 3.3 TD = 3n V2 TR = 2.5n 2 3.3 TF = 2.5n I1 PW = 2.5n PER = 10n -100u 0 Comparison table VCC = 3.3 V Measurement Simulation %Error Min VOH = (VCC - 0.2) V 3.1 3.1162 0.523 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 13. Low Level Output Voltage (2.7 V < VCC ≤ 3.6 V) Circuit simulation result 3.0V Output 2.0V 1.0V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q) Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V1 TC7PA175 V1 = 0 V3 V2 = 3.3 TD = 3n V2 TR = 2.5n 0.8 3.3 TF = 2.5n I1 PW = 2.5n PER = 10n 100u 0 Comparison table VCC = 3.3 V Measurement Simulation %Error VOL (V) 0.2 0.202436 1.218 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 14. High Level Output Voltage (2.3 V ≤ VCC ≤ 2.7 V) Circuit simulation result 2.5V 2.0V Output 1.0V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q) Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V1 TC7PA175 V1 = 0 V3 V2 = 2.5 TD = 3n V2 TR = 2.5n 1.6 2.5 TF = 2.5n I1 PW = 2.5n PER = 10n -100u 0 Comparison table VCC = 2.5 V Measurement Simulation %Error Min VOH = (VCC - 0.2) V 2.3 2.3156 0.678 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 15. Low Level Output Voltage (2.3 V ≤ VCC ≤ 2.7 V) Circuit simulation result 2.5V 2.0V Output 1.0V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q) Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V1 TC7PA175 V1 = 0 V3 V2 = 2.5 TD = 3n V2 TR = 2.5n 0.7 2.5 TF = 2.5n I1 PW = 2.5n PER = 10n 100u 0 Comparison table VCC = 2.5 V Measurement Simulation %Error VOL (V) 0.2 0.204523 2.262 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 16. High Level Output Voltage (1.8 V ≤ VCC 2.3 V) Circuit simulation result 1.5V Output 1.0V 0.5V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q) Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V1 TC7PA175 V1 = 0 V3 V2 = 1.8 TD = 3n V2 TR = 2.5n 1.26 1.8 TF = 2.5n I1 PW = 2.5n PER = 10n -100u 0 Comparison table VCC = 1.8 V Measurement Simulation %Error Min VOH = (VCC - 0.2) V 1.6 1.6062 0.387 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 17. Low Level Output Voltage (1.8 V ≤ VCC 2.3 V) Circuit simulation result 1.5V Output 1.0V 0.5V 0V 0.10us 0.25us 0.50us 0.75us 1.00us V(Q) Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V1 TC7PA175 V1 = 0 V3 V2 = 1.8 TD = 3n V2 TR = 2.5n 0.36 1.8 TF = 2.5n I1 PW = 2.5n PER = 10n 100u 0 Comparison table VCC = 1.8 V Measurement Simulation %Error VOL (V) 0.2 0.198028 -0.986 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 18. Propagation Delay Time (VCC = 1.8 V, CK-Q) Circuit simulation result 2.0V SEL>> 0V V(CLK) 2.0V 1.0V 0V V(D) 2.0V 1.0V 0V 20ns 30ns 40ns 50ns 60ns V(Q) tPLH tPHL Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V1 TC7PA175 V1 = 0 V3 V2 = 1.8 TD = 3n V2 TR = 2.5n V1 = 0 R1 C1 1.8 TF = 2.5n V2 = 1.8 PW = 2.5n TD = 0 500 30p PER = 10n TR = 2.5n TF = 2.5n PW = 7.5n PER = 20n 0 Comparison table CL = 30 pF, RL = 500 tr = tf =2 ns Measurement Simulation %Error tPLH (ns) 9.2 9.1611 -0.423 tPHL (ns) 9.2 9.1576 -0.461 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 19. Propagation Delay Time (VCC = 2.5 V, CK-Q) Circuit simulation result 3.0V 2.0V SEL>> 0V V(CLK) 3.0V 2.0V 1.0V 0V V(D) 2.0V 0V 10ns 20ns 30ns 40ns V(Q) tPLH t PHL Time Evaluation circuit CLK U2 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V3 TC7PA175 V1 = 0 V2 V2 = 2.5 TD = 1.5n V1 TR = 2.5n V1 = 0 R1 C1 2.5 TF = 2.5n V2 = 2.5 PW = 1n TD = 0 500 30p PER = 7n TR = 2.5n TF = 2.5n PW = 4.5n PER = 14n 0 Comparison table CL = 30 pF, RL = 500 tr = tf = 2 ns Measurement Simulation %Error tPLH (ns) 4.6 4.5742 -0.561 tPHL (ns) 4.6 4.5154 -1.839 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 20. Propagation Delay Time (VCC = 3.3 V, CK-Q) Circuit simulation result 4.0V 2.0V 0V V(CLK) 4.0V 2.0V 0V V(D) 4.0V SEL>> 0V 10ns 20ns 30ns 40ns V(Q) tPLH tPHL Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V3 TC7PA175 V1 = 0 V2 V2 = 2.7 TD = 1.5n V1 TR = 2.5n V1 = 0 R1 C1 3.3 TF = 2.5n V2 = 2.7 PW = 1n TD = 0 500 30p PER = 7n TR = 2.5n TF = 2.5n PW = 4.5n PER = 14n 0 Comparison table CL = 30 pF, RL = 500 tr = tf = 2 ns Measurement Simulation %Error tPLH (ns) 3.5 3.4162 -2.394 tPHL (ns) 3.5 3.4601 -1.140 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 21. Propagation Delay Time (VCC = 1.8 V, CLR -Q) Circuit simulation result 2.0V 1.0V SEL>> 0V V(U1:CLR) 2.0V 1.0V 0V 0s 50ns tPHL 100ns V(Q) Time Evaluation circuit U1 ___ CK CLR CK ___ GND CLR VCC D Q HI D Q Q V3 TC7PA175 V1 = 0 V2 V1 V2 = 1.8 TD = 5n R1 V1 = 1.8 TR = 2.5n C1 V2 = 0 TF = 2.5n 500 1.8 TD = 55n PW = 20n 30p TR = 2.5n PER = 100n TF = 2.5n PW = 1.5n PER = 60n 0 Comparison table CL = 30 pF, RL = 500 tr = tf = 2 ns Measurement Simulation %Error tPHL (ns) 9.2 9.1557 -0.482 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 22. Propagation Delay Time (VCC = 2.5 V, CLR -Q) Circuit simulation result 3.0V 2.0V 1.0V SEL>> 0V V(U1:CLR) 3.0V 2.0V 1.0V 0V 0s t 50ns PHL 100ns V(Q) Time Evaluation circuit U1 ___ CK CLR CK ___ GND CLR VCC D Q HI D Q Q TC7PA175 V3 V2 V1 V1 = 0 V2 = 2.5 R1 V1 = 2.5 TD = 5n C1 2.5 V2 = 0 TR = 2.5n 500 TD = 55n TF = 2.5n 30p TR = 2.5n PW = 20n TF = 2.5n PER = 100n PW = 0.1n PER = 60n 0 Comparison table CL = 30 pF, RL = 500 tr = tf = 2 ns Measurement Simulation %Error tPHL (ns) 4.6 4.5149 -1.850 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 23. Propagation Delay Time (VCC = 3.3 V, CLR -Q) Circuit simulation result 4.0V 2.0V SEL>> 0V V(U1:CLR) 4.0V 2.0V 0V 0s V(Q) 50ns tPHL 100ns Time Evaluation circuit U1 ___ CK CLR CK ___ GND CLR VCC D Q HI D Q Q V1 TC7PA175 V3 V1 = 2.7 V2 V2 = 0 V1 = 0 TD = 55n V2 = 2.7 R1 TR = 2.5n TD = 5n C1 3.3 TF = 2.5n TR = 2.5n 500 PW = 0.1n TF = 2.5n 30p PER = 60n PW = 20n PER = 100n 0 Comparison table CL = 30 pF, RL = 500 tr = tf = 2 ns Measurement Simulation %Error tPHL (ns) 3.5 3.494 -0.171 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 24. Minimum Setup Time and Minimum Hold time (ts, th, VCC = 1.8 V ) Circuit simulation result 2.0V SEL>> 0V V(CLK) 2.0V 1.0V 0V V(D) 2.0V tS th 1.0V H 0V 20ns 30ns 40ns 50ns 60ns V(Q) Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V1 TC7PA175 V1 = 0 V3 V2 = 1.8 TD = 3n V2 TR = 2.5n V1 = 0 R1 C1 1.8 TF = 2.5n V2 = 1.8 PW = 2.5n TD = 0 500 30p PER = 10n TR = 2.5n TF = 2.5n PW = 7.5n PER = 20n 0 Comparison table CL = 30 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output tS (ns) Min 3.0 3.0 Active th (ns) Min 3.0 13 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 25. Minimum Setup Time and Minimum Hold time (ts, th, VCC = 2.5 V ) Circuit simulation result 3.0V 2.0V SEL>> 0V V(CLK) 3.0V 2.0V 1.0V 0V V(D) 2.0V tS th H 0V 10ns 20ns 30ns 40ns V(Q) Time Evaluation circuit CLK U2 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V3 TC7PA175 V1 = 0 V2 V2 = 2.5 TD = 1.5n V1 TR = 2.5n V1 = 0 R1 C1 2.5 TF = 2.5n V2 = 2.5 PW = 1n TD = 0 500 30p PER = 7n TR = 2.5n TF = 2.5n PW = 4.5n PER = 14n 0 Comparison table CL = 30 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output tS (ns) Min 1.5 1.5 Active th (ns) Min 1.7 5.5 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 26. Minimum Setup Time and Minimum Hold time (ts, th, VCC = 3.3 V ) Circuit simulation result 4.0V 2.0V 0V V(CLK) 4.0V 2.0V 0V V(D) 4.0V tS th SEL>> 0V H 10ns 20ns 30ns 40ns V(Q) Time Evaluation circuit CLK U1 ___ CK CLR HI CK ___ GND CLR VCC D Q D Q D Q V3 TC7PA175 V1 = 0 V2 V2 = 2.7 TD = 1.5n V1 TR = 2.5n V1 = 0 R1 C1 3.3 TF = 2.5n V2 = 2.7 PW = 1n TD = 0 500 30p PER = 7n TR = 2.5n TF = 2.5n PW = 4.5n PER = 14n 0 Comparison table CL = 30 pF, RL = 500 tr = tf = 2 ns Measurement Simulation Output tS (ns) Min 1.5 1.5 Active th (ns) Min 1.7 5.5 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 27. Minimum Removal time (trem, VCC = 1.8 V ) Circuit simulation result 2.0V 1.0V 0V V(U1:CLR) 2.0V SEL>> 0V t V(U1:CK) rem 2.0V 1.0V 0V 2.5ns 10.0ns 20.0ns 30.0ns V(Q) Time Evaluation circuit U1 ___ CK CLR CK ___ GND CLR VCC D Q HI D Q Q TC7PA175 V3 V2 V4 V1 = 0 V2 = 1.8 R1 V1 = 1.8 TD = 7.1n C1 1.8 V2 = 0 TR = 2.5n TD = 0 TF = 2.5n 500 30p TR = 2.5n PW = 2.5n TF = 2.5n PER = 100n PW = 1.5n PER = 100n 0 Comparison table CL = 30 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output trem (ns) Min 3.1 3.1 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 28. Minimum Removal time (trem, VCC = 2.5 V ) Circuit simulation result 4.0V 2.0V 0V V(U2:CLR) 4.0V SEL>> 0V V(V3:+) 4.0V trem 2.0V 0V 2.5ns 10.0ns 20.0ns 30.0ns V(Q) Time Evaluation circuit U1 ___ CK CLR CK ___ GND CLR VCC D Q HI D Q Q V3 TC7PA175 V1 = 0 V2 V4 V2 = 2.5 TD = 6n V1 = 2.5 TR = 2.5n R1 C1 2.5 V2 = 0 TF = 2.5n TD = 0 PW = 2.5n 500 30p TR = 2.5n PER = 100n TF = 2.5n PW = 1.5n PER = 60n 0 Comparison table CL = 30 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output trem (ns) Min 2.0 2 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 29. Minimum Removal time (trem, VCC = 3.3 V ) Circuit simulation result 4.0V 2.0V 0V V(U2:CLR) 4.0V SEL>> 0V 4.0V V(V3:+) trem 2.0V 0V 2.5ns 10.0ns 20.0ns 30.0ns V(Q) Time Evaluation circuit U1 CK VCC CLK __ D CK D PR LO __ ___ PR _ PR CLR ___ Q CLR _ CLR Q Q GND Q Q TC7WZ74 V1 V2 V4 V3 V1 = 5 V1 = 5 R1 V1 = 5 V2 = 0 V2 = 0 C1 V2 = 0 TD = 15n 5 TD = 1.5n 500 TD = 0 TR = 3.8n TR = 3.8n 50p TR = 3.8n TF = 3.8n TF = 3.8n TF = 3.8n PW = 1.2n PW = 1.2n PW = 1.2n PER = 44n PER = 44n PER = 44n 0 Comparison table CL = 30 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output trem (ns) Min 1.5 1.5 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005