SPICE MODEL of TC7WZ74FU in SPICE PARK
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SPICE MODEL of TC7WZ74FU in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
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SPICE MODEL of TC7WZ74FU in SPICE PARK
- 1. Device Modeling Report COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT PART NUMBER : TC7WZ74FU MANUFACTURER : TOSHIBA Bee Technologies Inc. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 2. Truth Table Circuit simulation result U1:CLR 0 U1:PR 1 5.0V 2.5V 0V V(U1:CK) V(U1:D) 5.0V SEL>> 0V 0s 0.5us 1.0us 1.5us 2.0us V(U1:Q) V(U1:QBAR) Time Evaluation circuit DSTM1 U1 CLK CK VCC __ D CK OFFTIME = .2uS D PR HI __ ___ ONTIME = .2uS _ PR CLR ___ Q CLR LO _ Q Q GND Q TC7WZ74 V1 R1 1MEG 5 0 Comparison table Input Q Q %Error CLR PR D CK Measurement Simulation Measurement Simulation L H X X L L H H 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 3. Truth Table Circuit simulation result U1:CLR 1 U1:PR 0 5.0V 2.5V 0V V(U1:CK) V(U1:D) 5.0V SEL>> 0V 0s 0.5us 1.0us 1.5us 2.0us V(U1:Q) V(U1:QBAR) Time Evaluation circuit DSTM1 U1 CLK CK VCC __ D CK OFFTIME = .2uS D PR LO __ ___ ONTIME = .2uS _ PR CLR ___ Q CLR HI _ Q Q GND Q TC7WZ74 V1 R1 1MEG 5 0 Comparison table Input Q Q %Error CLR PR D CK Measurement Simulation Measurement Simulation H L X X H H L L 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 4. Truth Table Circuit simulation result U1:CLR 0 U1:PR 0 5.0V 2.5V 0V V(U1:CK) V(U1:D) 5.0V SEL>> 0V 0s 0.5us 1.0us 1.5us 2.0us V(U1:Q) V(U1:QBAR) Time Evaluation circuit DSTM1 U1 CLK CK VCC __ D CK OFFTIME = .2uS D PR LO __ ___ ONTIME = .2uS _ PR CLR ___ Q CLR LO _ Q Q GND Q TC7WZ74 V1 R1 1MEG 5 0 Comparison table Input Q Q %Error CLR PR D CK Measurement Simulation Measurement Simulation L L X X H H H H 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 5. Truth Table Circuit simulation result U1:CLR 1 U1:PR 1 U1:D 0 SEL>> 5.0V 2.5V 0V V(U1:CK) 5.0V 2.5V 0V 0s 0.5us 1.0us 1.5us 2.0us V(U1:Q) V(U1:QBAR) Time Evaluation circuit OFFTIME = .5uSDSTM2 U1 ONTIME = .5uS CLK CK VCC DELAY = 0.5u __ D CK STARTVAL = 0 LO D PR HI __ ___ OPPVAL = 1 _ PR CLR ___ Q CLR HI _ Q Q GND Q TC7WZ74 V1 R1 1MEG 5 0 Comparison table Input Q Q %Error CLR PR D CK Measurement Simulation Measurement Simulation H H L L L H H 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 6. Truth Table Circuit simulation result U1:CLR 1 U1:PR 1 U1:D 1 5.0V SEL>> 0V V(U1:CK) 5.0V 2.5V 0V 0s 0.5us 1.0us 1.5us 2.0us V(U1:Q) V(U1:QBAR) Time Evaluation circuit OFFTIME = .5uSDSTM2 U1 ONTIME = .5uS CLK CK VCC DELAY = 0.5u __ D CK STARTVAL = 0 HI D PR HI __ ___ OPPVAL = 1 _ PR CLR ___ Q CLR HI _ Q Q GND Q TC7WZ74 V1 R1 1MEG 5 0 Comparison table Input Q Q %Error CLR PR D CK Measurement Simulation Measurement Simulation H H H H H L L 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 7. Truth Table Circuit simulation result U1:CLR 1 U1:PR 1 U1:D 1 5.0V SEL>> 0V V(U1:CK) 5.0V 2.5V 0V 0s 0.5us 1.0us 1.5us 2.0us V(U1:Q) V(U1:QBAR) Time Evaluation circuit OFFTIME = .5uSDSTM2 U1 ONTIME = .5uS CLK CK VCC DELAY = 0 __ D CK STARTVAL = 0 HI D PR HI __ ___ OPPVAL = 1 _ PR CLR ___ Q CLR HI _ Q Q GND Q TC7WZ74 V1 R1 1MEG 5 0 Comparison table Input Q Q %Error CLR PR D CK Measurement Simulation Measurement Simulation H H X Qn Qn Qn Qn 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 8. High Level and Low Level Input Voltage (VCC = 1.8 V) Circuit simulation result 2.0V (575.010u,1.3502) Output 1.0V Input (525.008u,450.152m) 0V 0s 0.5ms 1.0ms 1.5ms 2.0ms V(Q) V(U1:CLR) Time Evaluation circuit U1 LO CK VCC __ D CK LO D PR __ ___ _ PR CLR ___ Q CLR QBAR _ Q Q GND Q Q TC7WZ74 V2 V3 V1 R2 V1 = 0 V1 = 1.8 R1 V2 = 1.8 V2 = 0 1.8 1G TD = 0.5m TD = 0.5m 1G TR = 0.1m TR = 0.1m TF = 0.1m TF = 0.1m PW = 1m PW = 1m PER = 2m PER = 2m 0 Comparison table VCC = 1.8 V Measurement Simulation %Error VIH (V) 1.35 1.3502 0.015 VIL (V) 0.45 0.450152 0.034 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 9. High Level and Low Level Input Voltage (VCC = 5 V) Circuit simulation result 5.0V (570.103u,3.5051) Output 2.5V Input (530.001u,1.5001) 0V 0s 0.5ms 1.0ms 1.5ms 2.0ms V(Q) V(U1:CLR) Time Evaluation circuit U1 LO CK VCC __ D CK LO D PR __ ___ _ PR CLR ___ Q CLR QBAR _ Q Q GND Q Q TC7WZ74 V2 V3 V1 R2 V1 = 0 V1 = 5 R1 V2 = 5 V2 = 0 5 1G TD = 0.5m TD = 0.5m 1G TR = 0.1m TR = 0.1m TF = 0.1m TF = 0.1m PW = 1m PW = 1m PER = 2m PER = 2m 0 Comparison table VCC = 5 V Measurement Simulation %Error VIH (V) 3.5 3.5051 0.146 VIL (V) 1.5 1.5001 0.007 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 10. High Level Output Voltage Circuit simulation result 5.0V Output 2.5V 0V 0s 5ms 10ms V(U1:Q) Time Evaluation circuit U1 HI CK VCC __ D CK HI D PR LO __ ___ _ PR CLR ___ Q CLR _ Q Q GND Q TC7WZ74 V2 V1 3.2 I1 4.5 -100u 0 Comparison table VCC = 4.5V Measurement Simulation %Error VOH (V) 4.5 4.499 -0.022 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 11. Low Level Output Voltage Circuit simulation result 5.0V Output 2.5V 0V 0s 5ms 10ms V(U1:Q) Time Evaluation circuit U1 HI CK VCC __ D CK HI D PR HI __ ___ _ PR CLR ___ Q CLR _ Q Q GND Q TC7WZ74 V2 V1 1 I1 4.5 100u 0 Comparison table VCC = 4.5V Measurement Simulation %Error VOL (V) 0 0 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 12. Propagation Delay Time (VCC = 1.8 V, CK-Q) Circuit simulation result 2.0V 1.0V 0V V(CLK) 2.0V 1.0V 0V V(D) 2.0V SEL>> 0V 20ns 30ns 40ns 50ns 60ns V(Q) tPLH tPHL Time Evaluation circuit CLK U3 CK VCC __ D CK D PR HI D __ ___ _ PR CLR ___ Q CLR HI _ Q Q GND Q Q V3 TC7WZ74 V1 V1 = 0 V1 = 0 V2 V2 = 1.8 V2 = 1.8 TD = 3.4n TD = 0 TR = 3.8n TR = 3.8n R1 C1 1.8 TF = 3.8n TF = 3.8n PW = 2.5n PW = 8.33n 1MEG 15p PER = 12.1n PER = 24.2n 0 Comparison table CL = 15 pF, RL = 1 MEG tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 10 10.090 0.900 tPHL (ns) 10 10.140 1.400 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 13. Propagation Delay Time (VCC = 2.5 V, CK-Q) Circuit simulation result 2.0V 1.0V 0V V(CLK) 2.0V 1.0V 0V V(D) 2.0V SEL>> 0V 20ns 40ns 60ns 70ns V(Q) tPLH tPHL Time Evaluation circuit CLK U3 CK VCC __ D CK D PR HI D __ ___ _ PR CLR ___ Q CLR HI _ Q Q GND Q Q V3 TC7WZ74 V1 V1 = 0 V1 = 0 V2 V2 = 2.5 V2 = 2.5 TD = 3.4n TD = 0 TR = 3.8n TR = 3.8n R1 C1 2.5 TF = 3.8n TF = 3.8n PW = 1.3n PW = 6.4n 1MEG 15p PER = 10.2n PER = 20.4n 0 Comparison table CL = 15 pF, RL = 1 MEG tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 4.9 4.9625 1.276 tPHL (ns) 4.9 4.9357 0.729 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 14. Propagation Delay Time (VCC = 3.3 V, CK-Q) Circuit simulation result 4.0V 2.0V 0V V(CLK) 4.0V 2.0V 0V V(D) 4.0V SEL>> 0V 20ns 40ns 60ns 70ns V(Q) tPLH tPHL Time Evaluation circuit CLK U3 CK VCC __ D CK D PR HI D __ ___ _ PR CLR ___ Q CLR HI _ Q Q GND Q Q V3 TC7WZ74 V1 V1 = 0 V1 = 0 V2 V2 = 3.3 V2 = 3.3 TD = 2.1n TD = 0 TR = 3.8n TR = 3.8n R1 C1 3.3 TF = 3.8n TF = 3.8n PW = 1.3n PW = 6.43n 500 50p PER = 10.2n PER = 20.4n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 4.3 4.3083 0.193 tPHL (ns) 4.3 4.3984 2.288 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 15. Propagation Delay Time (VCC = 5 V, CK-Q) Circuit simulation result 5.0V 2.5V 0V V(CLK) 5.0V 2.5V 0V V(D) 5.0V SEL>> 0V 20ns 40ns 60ns 70ns V(Q) Time tPLH tPHL Evaluation circuit CLK U3 CK VCC __ D CK D PR HI D __ ___ _ PR CLR ___ Q CLR HI _ Q Q GND Q Q V3 TC7WZ74 V1 V1 = 0 V1 = 0 V2 V2 = 5 V2 = 5 TD = 1.5n TD = 0 TR = 3.8n TR = 3.8n R1 C1 5 TF = 3.8n TF = 3.8n PW = 1.3n PW = 6.4n 500 50p PER = 10.2n PER = 20.4n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 2.8 2.8216 0.771 tPHL (ns) 2.8 2.8606 2.164 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 16. Propagation Delay Time (VCC = 1.8 V, CLR , PR -Q) Circuit simulation result 2.0V 1.0V Output 0V V(CLR) Input 2.0V Input SEL>> 0V V(PR) tPHL tPLH 2.0V 1.0V 0V 40ns 60ns 80ns 100ns 120ns V(Q) Time Evaluation circuit U1 LO CK VCC __ D CK D PR LO __ ___ PR _ PR CLR ___ Q CLR _ CLR Q Q GND Q Q TC7WZ74 V1 V2 V3 V1 = 1.8 R1 V1 = 1.8 V2 = 0 C1 V2 = 0 TD = 15n 1.8 1MEG TD = 0 TR = 3.8n 15p TR = 3.8n TF = 3.8n TF = 3.8n PW = 1.2n PW = 1.2n PER = 44n PER = 44n 0 Comparison table CL = 15 pF, RL = 1 MEG tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 10 10.194 1.940 tPHL (ns) 10 10.144 1.440 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 17. Propagation Delay Time (VCC = 2.5 V, CLR , PR -Q) Circuit simulation result 4.0V 2.0V Output 0V V(CLR) Input 4.0V Input SEL>> 0V V(PR) tPHL tPLH 4.0V 2.0V 0V 40ns 60ns 80ns 100ns 120ns V(Q) Time Evaluation circuit U1 CK VCC __ D CK D PR LO __ ___ PR _ PR CLR ___ Q CLR _ CLR Q Q GND Q Q TC7WZ74 V1 V2 V3 V1 = 2.5 V1 = 2.5 V2 = 0 R1 C1 V2 = 0 TD = 15n 2.5 TD = 0 TR = 3.8n 1MEG 15p TR = 3.8n TF = 3.8n TF = 3.8n PW = 1.2n PW = 1.2n PER = 44n PER = 44n 0 Comparison table CL = 15 pF, RL = 1 MEG tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 5 5.0575 1.150 tPHL (ns) 5 5.03 0.600 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 18. Propagation Delay Time (VCC = 3.3 V, CLR , PR -Q) Circuit simulation result 4.0V 2.0V Output 0V V(CLR) Input 4.0V Input 2.0V 0V V(PR) tPHL tPLH 4.0V SEL>> 0V 40ns 60ns 80ns 100ns 120ns V(Q) Time Evaluation circuit U1 CK VCC __ D CK D PR LO __ ___ PR _ PR CLR ___ Q CLR _ CLR Q Q GND Q Q TC7WZ74 V1 V2 V3 V1 = 3.3 V1 = 3.3 V2 = 0 R1 C1 V2 = 0 TD = 15n 3.3 TD = 0 TR = 3.8n 500 50p TR = 3.8n TF = 3.8n TF = 3.8n PW = 1.2n PW = 1.2n PER = 44n PER = 44n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 4.3 4.3112 0.260 tPHL (ns) 4.3 4.2971 -0.067 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 19. Propagation Delay Time (VCC = 5 V, CLR , PR -Q) Circuit simulation result 5.0V SEL>> Output 0V Input V(CLR) 5.0V 2.5V 0V V(PR) t PHL tPLH 5.0V 2.5V 0V 40ns 60ns 80ns 100ns 120ns V(Q) Time Evaluation circuit U1 LO CK VCC __ D CK D PR LO __ ___ PR _ PR CLR ___ Q CLR _ CLR Q Q GND Q Q TC7WZ74 V1 V2 V3 V1 = 5 R1 V1 = 5 V2 = 0 C1 V2 = 0 TD = 15n 5 500 TD = 0 TR = 3.8n 50p TR = 3.8n TF = 3.8n TF = 3.8n PW = 1.2n PW = 1.2n PER = 44n PER = 44n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 3.1 3.1267 0.861 tPHL (ns) 3.1 3.1617 1.990 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 20. Minimum Setup Time and Minimum Hold time (ts, th, VCC = 2.5 V ) Circuit simulation result 2.0V 1.0V 0V V(CLK) 2.0V 1.0V 0V V(D) 2.0V S t th SEL>> H 0V 20ns 40ns 60ns 70ns V(Q) Time Evaluation circuit CLK U3 CK VCC __ D CK D PR HI D __ ___ _ PR CLR ___ Q CLR HI _ Q Q GND Q Q V3 TC7WZ74 V1 V1 = 0 V1 = 0 V2 V2 = 2.5 V2 = 2.5 TD = 3.4n TD = 0 TR = 3.8n TR = 3.8n R1 C1 2.5 TF = 3.8n TF = 3.8n PW = 1.3n PW = 6.4n 1MEG 15p PER = 10.2n PER = 20.4n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output tS (ns) Min 3.4 3.4 Active th (ns) Min 2.4 6.7998 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 21. Minimum Setup Time and Minimum Hold time (ts, th, VCC = 3.3 V ) Circuit simulation result 4.0V 2.0V 0V V(CLK) 4.0V 2.0V 0V V(D) 4.0V tS th SEL>> 0V H 20ns 40ns 60ns 70ns V(Q) Time Evaluation circuit CLK U3 CK VCC __ D CK D PR HI D __ ___ _ PR CLR ___ Q CLR HI _ Q Q GND Q Q V3 TC7WZ74 V1 V1 = 0 V1 = 0 V2 V2 = 3.3 V2 = 3.3 TD = 2.1n TD = 0 TR = 3.8n TR = 3.8n R1 C1 3.3 TF = 3.8n TF = 3.8n PW = 1.3n PW = 6.43n 500 50p PER = 10.2n PER = 20.4n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output tS (ns) Min 2.1 2.1 Active th (ns) Min 1.4 8.1302 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 22. Minimum Setup Time and Minimum Hold time (ts, th, VCC = 5 V ) Circuit simulation result 5.0V 2.5V 0V V(CLK) 5.0V 2.5V 0V V(D) 5.0V tS SEL>> 0V th 20ns H 40ns 60ns 70ns V(Q) Time Evaluation circuit CLK U3 CK VCC __ D CK D PR HI D __ ___ _ PR CLR ___ Q CLR HI _ Q Q GND Q Q V3 TC7WZ74 V1 V1 = 0 V1 = 0 V2 V2 = 5 V2 = 5 TD = 1.5n TD = 0 TR = 3.8n TR = 3.8n R1 C1 5 TF = 3.8n TF = 3.8n PW = 1.3n PW = 6.4n 500 50p PER = 10.2n PER = 20.4n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output tS (ns) Min 1.5 1.5 Active th (ns) Min 1.0 8.7 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 23. Minimum Removal time (trem, VCC = 2.5 V ) Circuit simulation result 3.0V 0V V(CLR) V(CLK) 3.0V trem 0V V(PR) 3.0V SEL>> 0V 20ns 40ns 60ns 80ns 100ns V(Q) Time Evaluation circuit U1 CK VCC CLK __ D CK D PR LO __ ___ PR _ PR CLR ___ Q CLR _ CLR Q Q GND Q Q TC7WZ74 V1 V2 V4 V3 V1 = 2.5 V1 = 2.5 R1 V1 = 2.5 V2 = 0 V2 = 0 C1 V2 = 0 TD = 15n 2.5 TD = 3.6n 500 TD = 0 TR = 3.8n TR = 3.8n 50p TR = 3.8n TF = 3.8n TF = 3.8n TF = 3.8n PW = 1.2n PW = 1.2n PW = 1.2n PER = 44n PER = 44n PER = 44n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output trem (ns) Min 3.6 3.6 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 24. Minimum Removal time (trem, VCC = 3.3 V ) Circuit simulation result 4.0V SEL>> 0V V(CLR) V(CLK) 4.0V trem 2.0V 0V V(PR) 3.0V 0V 20ns 40ns 60ns 80ns 100ns V(Q) Time Evaluation circuit U1 CK VCC CLK __ D CK D PR LO __ ___ PR _ PR CLR ___ Q CLR _ CLR Q Q GND Q Q TC7WZ74 V1 V2 V4 V3 V1 = 3.3 V1 = 3.3 R1 V1 = 3.3 V2 = 0 V2 = 0 C1 V2 = 0 TD = 15n 3.3 TD = 2.2n 500 TD = 0 TR = 3.8n TR = 3.8n 50p TR = 3.8n TF = 3.8n TF = 3.8n TF = 3.8n PW = 1.2n PW = 1.2n PW = 1.2n PER = 44n PER = 44n PER = 44n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output trem (ns) Min 2.2 2.2 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 25. Minimum Removal time (trem, VCC = 5 V ) Circuit simulation result 5.0V SEL>> 0V V(CLR) V(CLK) trem 5.0V 2.5V 0V V(PR) 3.0V 0V 20ns 40ns 60ns 80ns 100ns V(Q) Time Evaluation circuit U1 CK VCC CLK __ D CK D PR LO __ ___ PR _ PR CLR ___ Q CLR _ CLR Q Q GND Q Q TC7WZ74 V1 V2 V4 V3 V1 = 5 V1 = 5 R1 V1 = 5 V2 = 0 V2 = 0 C1 V2 = 0 TD = 15n 5 TD = 1.5n 500 TD = 0 TR = 3.8n TR = 3.8n 50p TR = 3.8n TF = 3.8n TF = 3.8n TF = 3.8n PW = 1.2n PW = 1.2n PW = 1.2n PER = 44n PER = 44n PER = 44n 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation Output trem (ns) Min 1.3 1.5 Active All Rights Reserved Copyright (c) Bee Technologies Inc. 2005