This document discusses a course on superscalar processor design taught at Carnegie Mellon University since 1995. The course objectives are to teach modern processor design skills at the microarchitecture level, cover techniques for achieving high performance through instruction-level parallelism, and impart insights for designing high-performance microprocessors. The course also includes a project to design a future-generation superscalar microprocessor. Additional posts will provide solutions to exercises from the textbook "Modern Processor Design" by John Paul Shen and Mikko H. Lipasti.

1. Solution Manual for Modern Processor Design by John Paul
Shen and Mikko H. Lipasti
This book emerged from the course Superscalar Processor Design, which has been taught at
Carnegie Mellon University since 1995. Superscalar Processor Design is a mezzanine course targeting
seniors and first-year graduate students. Quite a few of the more aggressive juniors have taken the
course in the spring semester of their junior year. The prerequisite to this course is the
Introduction to Computer Architecture course. The objectives for the Superscalar Processor Design
course include: (1) to teach modem processor design skills at the microarchitecture level of
abstraction; (2) to cover current microarchitecture techniques for achieving high performance
via the exploitation of instruction-level parallelism (ILP); and (3) to impart insights and hands-on
experience for the effective design of contemporary high-performance microprocessors for mobile,
desktop, and server markets. In addition to covering the contents of this book, the course contains
a project component that involves the microarchitectural design of a future-generation superscalar
microprocessor.
Here, in next successive posts, I am going to post solutions for the same Text-book (Modern
Processor Design by John Paul Shen and Mikko H. Lipasti). If you find any difficulty or wants to
suggest anything, feel free to comment...:)
Link:
http://targetiesnow.blogspot.in/p/solution-manual-for-modern-
processor.html
Modern Processor Design by John Paul Shen and Mikko H.
Lipasti : Exercise 1.6 and 1.7 Solution

2. Q.1.6: A program's run time is determined by the product of instructions per program, cycles
per instruction, and clock frequency. Assume the following instruction mix for a MlPS-like RISC
instruction set: 15% stores, 25% loads, 15% branches, and 35% integer arithmetic, 5% integer shift,
and 5% integer multiply. Given that load instructions require two cycles, branches require four
cycles, integer ALU instructions require one cycle, and integer multiplies require ten cycles,
compute the overall CPI.
Q.1.7: Given the parameters of Problem 6, consider a strength-reducing optimization that
converts multiplies by a compile-time constant into a sequence of shifts and adds. For this
instruction mix, 50% of the multiplies can be converted to shift-add sequences with an average
length of three instructions. Assuming a fixed frequency, compute the change in instructions per
program, cycles per instruction, and overall program speedup.
Solution: http://targetiesnow.blogspot.in/2013/11/modern-processor-design-byjohn-paul_9765.html#links
Q.2.4: Consider that you would like to add a load-immediate instruction to the TYP instruction
set and pipeline. This instruction extracts a 16-bit immediate value from the instruction word, signextends the immediate value to 32 bits, and stores the result in the destination register specified in
the
instruction
word.
Since
the
extraction
and
sign-extension
can
be
accomplished without the ALU, your colleague suggests that such
instructions be
able to
write their results into
the
register in the
decode (ID)
stage.
Using the
hazard
detection algorithm described in Figure 2-15, identify what additional hazards such a change might
introduce.
Q.2.5: Ignoring
pipeline interlock hardware (discussed in Problem 6), what additional
pipeline resources does the change outline in Problem 4 require? Discuss these resources and
their cost.
Q.2.6: Considering
the change outlined in Problem 4, redraw the pipeline interlock
hardware shown in Figure 2-18 to correctly handle the load-immediate instructions.
Solution:
processor.html
http://targetiesnow.blogspot.in/2013/11/ex-24-25-26-solution-modern-

3. Ex 1.8, 1.9 and 1.10 Solution: Modern Processor Design by
John Paul Shen and Mikko H. Lipasti :
Q.1.8: Recent processors like the Pentium 4 processors do not implement single-cycle shifts.
Given the scenario of Problem 7, assume that s = 50% of the additional integer and shift
instructions introduced by
strength reduction are
shifts,
and shifts now take
four cycles to execute. Recompute the cycles per instruction and overall program speedup. Is
strength reduction still a good optimization?
Q.1.9: Given the assumptions of Problem 8, solve for the break-even ratio s (percentage of
additional instructions that are shifts). That is, find the value of s (if any) for which program
performance is identical to the baseline case without strength reduction (Problem 6).
Q.1.10: Given the assumptions of Problem 8, assume you are designing the shift unit on the
Pentium 4 processor. You have concluded there are two possible implementation options for the
shift unit: 4-cycle shift latency at a frequency of 2 GHz, or 2-cycle shift latency at 1.9 GHz. Assume
the rest of the pipeline could run at 2 GHz, and hence the 2-cycle shifter would set the entire
processor’s frequency to 1.9 GHz. Which option will provide better overall performance?
Solution:
john-paul_13.html
http://targetiesnow.blogspot.in/2013/11/modern-processor-design-by-