Session 01 v.3

• Click to edit Master text styles
– Second level
• Third level
– Fourthg i t a l D e s i g n u s i n g V H D L
D i level
Session One
» Fifth level

Introduced by

Cairo-Egypt

Version 03 – June 2012

about Start Group

Mahmoud Abdellatif
– Second level
Alaa Salah Shehata
Mohamed level
• Third Salah
Mohamed Talaat
– Fourth level
» Fifth level
start.courses@gmail.com www.slideshare.net/StartGroup

www.facebook.com/groups/start.group

www.startgroup.weebly.com

+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011
+ 02 0128-0090250 A.S

Session One 2

Outline

• Click to edit Master Introduction to VHDL
– Second level
• Third level
text styles
ASIC and FPGA Design flow

How to Read VHDL Code
1
– Fourth level
Demo no.1 Using ModelSim SE and Xilinx ISE
» Fifth level

Session One 3

text styles
– Second level ASIC and FPGA Design flow

• Third level How to Read VHDL Code
– Fourth level
» Fifth level

Session One 4

What Is Digital Design !!

Digital hardware has experienced large expansion and improvement in the past 40 years. Since its
introduction, the number of transistors in a single chip has grown exponentially, and a silicon chip
– Second level
now contains hundreds of millions of transistors.

• Third level
On Digital world, based on logic, all things are 1 or 0 based on logic basics, all analogue world
should be quantized to levels "Digits ”.
– Fourth level
Applications of digital hardware level
» Fifth
Digital Computational Circuits *ALUs, Dividers, Multipliers…..+
Digital Communications blocks
Digital Control
Digital Interfaces *USB, PS2, …..+
Digital Signal Processing [DSP]

Session One 5

Designing with Boolean Equations

It would be hard to design any digital system without understanding the basic building blocks
as gates and flip-flops.

– Second level
Boolean equations are impractical for large design containing hundreds of flip flops because it
could result in a huge number of logical equations.
• Third level
– Fourth level
» Fifth level

X= A.B

Session One 6

Schematic based design

-Schematic based design expanded the
– Second level
capabilities of Boolean equations.
-Delays and area considerations are important
• Third
and take place here. level

– Fourth level
-The major drawback of traditional design
methods is the manual translation of design
» Fifth level
description into a set of logical equations.

-This step can be entirely eliminated with
hardware description languages (HDLs).

Session One 7

Hardware Description Language [HDL]

Question:
– Second level
How do we know that we have not made a mistake
when we manually draw a schematic and connect
• Third level
components to implement a function?

Answer: – Fourth level
By describing the design Fifth level [such as
» in a high-level
(c, basic…)+ language, we can simulate our design
before we manufacture it. This allows us to catch
design errors, i.e., that the design does not work as
we thought it would.

• Simulation guarantees that the design behaves as it
should.
HDL is short for Hardware Description Language

Session One 8

What is VHDL ?

• Click toIntegrated Master text styles
-Very High Speed
edit Circuit Hardware Description Language
– Second level developed by the U.S. Department of Defense
-Early 1980s : It was
• Third level
-1987 : IEEE Std 1076 - 87
-1993 : Added some new features and became IEEE Std 1076 – 93
-1999– An extension to the language called VHDL – AMS
: Fourth level
-2008: IEEE» Fifth level (New features)
Std 1076 – 2008

Session One 9

text styles

– Fourth level
» Fifth level

Session One 10

ASIC and FPGA Design Flow

Specifications System Level
Design

– Second level
• Third level Function
RTL Description
– Fourth level Verification
» Fifth level
Gate Level
Synthesis
Simulation

Place
&Route

Fabrication Configuration
ASIC FPGA

Session One 11

ASIC and FPGA Design Flow

• Click to edit Masteroftext styles designing the system
Specification is an set requirements before

RTL Description Register-Transfer Level (RTL)
– Second level Designing using HDL which should be synthesizable

• Third
Function Verification level Does this proposed design do what is intended?
– Fourth level Functionality of your RTL
Test

Synthesis » Fifth level
Convert RTL description into a H/W.
You need to Verify that your RTL can be converted into hardware

Placement Deciding where to place all electronic components.

Routing Wiring the placed components

This last two steps depend on the rules and limitations of the manufacturing process.

Session One 12

ASIC vs FPGA

Verilog and VHDL are Hardware Description languages that are used to write programs for
electronic that do not share a computer’s basic architecture.

– Second level
FPGAs ASICs

• Third level Programmable Gate Array
Field Application Specific Integrated
Circuit
– Fourth level
Re-Design CAN reprogrammable integrated CANNOT specific application
» Fifth level
circuit
Main Purpose Design and Test and Implementation Implementation
Area Wastes material Little wastes material

Low Volume Better Expensive
Production

Session One 13

FPGAs

Field-Programmable Gate Arrays
– Pre-fabricated silicon devices that comprise of an array of uncommitted circuit elements
(logic blocks) and interconnect resources.
– Second level
– An IC designed to be configured by end-user after manufacturing

Implement• Third level that ASIC can perform
any logical function
– Fourth level
Applications:
– DSP » Fifth level
– Device controllers
– Medical imaging

Session One 14

VHDL vs Verilog

Verilog and VHDL are Hardware Description languages that are used to
Why do we Use
write programs for electronic that do not share a computer’s basic VHDL !!
architecture mainly FPGAs.
– Second level
Verilog VHDL

History • Third level on C
Based Older based on Pascal and Ada
Data Types very simple
– Fourth level strongly typed allows creating complex data types

case sensitivity » Fifth sensitive
case level case insensitive

Session One 15

HDL vs Programming Languages

HDL Programming Languages
• Examples to edit Master text styles JAVA, …..
Click VHDL, Verilog, System C C, C#,
– Second level
Purpose Hardware Software
[Digital Logic] [Binary Executable]
• Third
Development level
Compile for Simulation Only compile
– Fourth level for Hardware
Synthesis
Debugging » Fifth level and see waveforms
Simulation Execute & See results text or graphic

Statements Concurrent and Sequential Sequential Only

Session One 16

VHDL Language Scope

There is two types of tools that deal with VHDL

– Second level
-Simulation (Used all programming language
capabilities )
• Third using
to test the logic designlevel simulation models “All
Language syntax used’’
– Fourth level
-Synthesis (Hardware)» Fifth level
to convert codes to hardware “pare of Language
syntax used”

IEEE 1076 IEEE 1076
Synthesis MODELING

Session One 17

text styles

– Fourth level
» Fifth level

Session One 18

Library and Package

VHDL libraries allow you to store commonly used packages and entities that you can use in your VHDL
files.
Library and Packages define special types used in a project.
– Second level
• Third level
–
LIBRARY ieee; Fourth level
USE ieee.std_logic_1164.all;
USE ieee………… » Fifth level
..

Session One 19

Design Units

• are two types ofedit units in VHDL text styles
There
Click to design Master
– Not dependent upon other design units
–Primary
Second level
• Third level
Entity (Interface)
How the system will communicate with the outside world
?
– Fourth level
» Fifth level
–Secondary
Depends on primary design unit
Architecture (Function )
–What the system should do ?

-No secondary can exist as stand-alone—without the primary
-Whenever the primary design unit changes, the secondary design must be reanalyzed

Session One 20

Entity

Define ports (inputs and outputs) of the module

i.e the interface of the block

Entity Declaration
– Second level
ENTITY architecture_name IS
PORT( • Third level
port_name : mode type;
– Fourth mode
port_name : level type;
port_name Fifth level type
» : mode
);
END entity_name;

Session One 21

- <entity_name> Define the model name
- <port_name>
Define the port name
– VHDL is case Insensitive ----- Important of the port with Underscore _ or number
-
-
Second port name or entity name Note
Don’t start the
level
• Third level
- <mode> Define the port direction
IN
– Fourth levelfrom it
: Only read
OUT » Fifth level
: Only write on it
INOUT : read from or write on it (controlled by another signal)

<type> Define the port data type
--------------------------------------------------------------------------------------------
- Last port has no semicolon ;
- Line Comments started by - -
- Comma , can separate ports with the same type and mode
- A,b : in bit ;

22

Example 01

Entity of 2-input AND Gate
– Second level
LIBRARY ieee;
A
• Third level AND_GATE C
B
– Fourth
ENTITY AND_GATE IS level
PORT (
» Fifth level
a : in BIT;
b : in BIT;
C : out BIT
);
END ENTITY AND_GATE ;

Session One 23

Question !!

System A is composed of system B,C and D.
Determine the entity of system A?

– Second level
• Third level
– Fourth level
» Fifth level

Session One 24

Question !!

System A is composed of system B,C and D.
Determine the entity of system A?

– Second level
• Third level
– Fourth level
» Fifth level
Entity A

Session One 25

Basic data types

VHDL i s s t r o n g l y t y p e d
• Click to BIT Master text styles
edit STD_LOGIC
– Second level
0 1 0 1 H L U
• Third level
– Fourth level
Default X W Z - Default
value » Fifth level value
BIT_VECTOR :
1D-array each element of the BIT type STD_LOGIC_VECTOR :
1D-array each element of the STD_LOGIC type
Example: Example:

a : in BIT; a : in STD_LOGIC;
b : in BIT_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0);
c : in BIT_VECTOR (0 to 3); c : in STD_LOGIC_VECTOR(0 to 3);

Session One 26

Basic data types

• XClick to edit Master text styles
Z 0 1 U
– Second level
Unknown High Strong Strong UnIitialized
• ThirdImpedance
MULTIPLE DEVICE More than level Zero One
Default value
value assigned in same signal
– Fourth level
W -
» Fifth level H L

Weak Don’t Weak Weak
Unknown care One Zero

To define std_logic data type

LIBRARY ieee;
USE ieee.std_logic_1164 .all;

Session One 27

Basic data types

VHDL is strongly typed
• Click to BIT Master text styles
edit STD_LOGIC
– Second level
0 1 0 1 H L U
• Third level
– Fourth level
Default X W Z - Default
value » Fifth level value
BIT_VECTOR : Use std_logic
1D-array each element of the BIT type STD_LOGIC_VECTOR :
1D-array each element of the STD_LOGIC type
Example: Example:

a : in BIT; a : in STD_LOGIC;
b : in BIT_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0);
c : in BIT_VECTOR (0 to 3); c : in STD_LOGIC_VECTOR(0 to 3);

Session One 28

Example 02

Entity of 2-input AND Gate using STD_LOGIC
– Second level
LIBRARY ieee;
A
• Third level AND_GATE C
B
– Fourth
ENTITY AND_GATE IS level
PORT (
» Fifth level
a : in STD_LOGIC;
b : in STD_LOGIC;
C : out STD_LOGIC
);

Session One 29

Architecture

Describe the operation (relations between inputs and outputs) of the module
i.e the Body of the block

– Second level
Architecture Declaration

• Third level
ARCHITECTURE architecture_name OF entity_name IS
--architecture declaration discussed later
BEGIN – Fourth level
--architectureFifth level
» body
END architecture_name ;

Non-Blocking Assignment <=
To assign operations on inputs into an output the non-blocking assignment is used
-the LHS -> Outputs only as we write on it
-the RHS -> Inputs only as we read from it
C <= A and B ; C <= “01010..0”;
--can make operations on RHS -- on std_logic_vector
C <= „1‟; or c <= „0‟; to C(1) <= „1‟;
--assign values on std_logic C(2downto 1 ) <= „1‟;
Session One 30

Example 03

2-input AND Gate
LIBRARY ieee;
– Second level
A
• Third IS
ENTITY AND_GATE level AND_GATE C
PORT ( B
a : – Fourth level
in STD_LOGIC;
b : in STD_LOGIC;
» Fifth level
C : out STD_LOGIC
);

ARCHITECTURE behave OF AND_GATE
IS
BEGIN
c <= a and b;
--non blocking assignment
END behave;
Session One 31

Example 04

N-bits 2-input AND Gate
Packages
Libraries

LIBRARY ieee;
– Second level
&

A
• AND_GATE IS
ENTITY Third level
AND_GATE
C
(input/output ports)

B
Interface definition

PORT ( – Fourth level
a : in std_logic_vector (3 downto 0);
b : in Fifth level
» std_logic_vector (3 downto 0);
C : out std_logic_vector (3 downto 0)
);

ARCHITECTURE behave OF AND_GATE IS
Functional/behavioral
Implementation

BEGIN
c <= a and b;
--non blocking assignment
END behave;

Session One 32

text styles

– Fourth level
» Fifth level

Session One 33

Demo 01
ModelSim Setup
Using Modelsim SE and Xilinx ISE
Installation Steps
Writing code that describe the Entity and Architecture of 2-XOR Gate .
– Second level
Simulating it on Modelsim and using Xilinx ISE synthesis tool.

• Third level
Tools : Modelsim SE / Xilinx ISE
– Fourth level
Goal : Be familiar with tools before using it.
Code : attached. » Fifth level

A
XOR C
B

Session One 34

Summary

• VHDL is StronglyeditHardware Description Language.
- Click to typed Master text styles
- There are two basic design units to build your model
– Second level
- Entity : Define your model interface.
- Architecture : Define operation of this model.
- • Third level
ASIC and FPGA design flow
– Fourth level
- Specifications
- RTL
» Fifth level
- Verification (modeling)
- Synthesis (hardware)
- Gate Level Simulation
- Place and Route
- Configuration

Session One 35

Time for Your Questions

– Second level
• Third level
– Fourth level
» Fifth level

Session One 36

Download Session 01 Files

Read Session-1 Notes carefully to be ready for the next session’s QUIZ

–Demo_1 www.startgroup.weebly.com/vhdl-examples.html
Second level
• Third level
Download tools :
– Fourth level
• Xilinx ISE WebPACK (Free)
http://www.xilinx.com/support/download/index.htm
» Fifth level
• ModelSim SE
http://model.com/content/modelsim-se-downloads-support

Session One 37

Take Your Notes
Print the slides and take your notes here
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See You Next Session .. Don’t miss


Thank
– Second level
• Third level
– Fourth level

You
» Fifth level

Session 01 v.3

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