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# Session 03 v.3

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### Session 03 v.3

1. 1. • Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session Three » Fifth level Introduced by Cairo-Egypt Version 03 – June 2012 1
2. 2. about Start Group• Click to edit Master text styles Mahmoud Abdellatif – Second level Alaa Salah Shehata Mohamed level • Third Salah Mohamed Talaat – Fourth level » Fifth level start.courses@gmail.com www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com Start.courses@gmail.com + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S Session Three 2
3. 3. Lab 02• Click to edit Master text stylesTitle: Simulation of a Register on Modelsim – Second levelGoal: •  Third level synchronous sequential circuits Be familiar with  Solution of last session Assignment – Fourth level » Fifth level Session Three 3
4. 4. Lab 02 • Click to edit Master text stylesRegisterLibrary ieee; D Q – Second leveluse ieee.std_logic_1164.all;Entity d_ff is Reset Register Q’ Port( d, clk, rst : in std_logic; • Third level Q,Q_inv : out std_logic);end entity; – Fourth levelArchitecture behav of d_ff is clk Signal Q_sig : std_logic; » Fifth levelBegin process(clk, rst) begin If (rst = 1) then Q_sig <= 0; elsif rising_edge(clk) then Q_sig <= d; end if; end process; Q <= Q_sig; Q_inv <= not Q_sig;end behav; Session Three 4
5. 5. Outline• Click to edit Master text styles Statement – Second level • Third level Concurrent Statements 1-Assign 2-Process 3-When-else 4-With-select 3 – Fourth level Data Objects » Fifth level 1-Signals 2-Variables 3-Constants Session Three 5
6. 6. Outline• Click to edit Master text styles Statement Concurrent Statements 1-Assign – Second level 2-Process 3-When-else • Third level 4-With-select – Fourth level Data Objects » Fifth level 1-Signals 2-Variables 3-Constants Session Three 6
7. 7. VHDL Statements• Click to edit Master Assignment text styles – Second level Concurrent Process • Third level When-Else – Fourth level With-Select Statements » Fifth level IF CASE Sequential FOR WAIT Session Three 7
8. 8. Concurrency ConceptWe can consider any system to be consisted of many blocks each has a specific• Click to edit Master text stylesfunction and work together concurrently (in parallel) to form the wholefunction. – Second levelAs VHDL is a Hardware Description Language so the default statements in VHDL • Third levelare those who are executed in parallel. – are called Concurrent statements.These statementsFourth level » Fifth level Session Three 8
9. 9. Concurrent Statements [1-Assign <=]- Assignments relating outputs to inputs• Click to edit Master text styles- Non Blocking Assignment <= is used- Assign statements can be written in any order. – Second levelIn this Example, the value of x depends on a AND b, whenever a/b changes x will • Third levelchange accordingly – Fourth levelSimilarly the value of yFifthalways change whenever c/d changes » will levelIt might happen that the value of x changes at the same time the value of y changes -> Both changes happen concurrently a xbegin x <= a AND b; b y <= c AND d; e c e <= x AND y;end rtl; y d Session Three 9
10. 10. Concurrent Statements [2-Process] • Click to edit Master text styles Process allows writing sequential statements within concurrent environment – declaration Process Second level 21 • Name> : PROCESS (sensitivity list) 3 <Process Third level -- process declaration; 45 Begin – Fourth level » Fifth level -- sequential statements ; 67 End PROCESS <Process Name> ; 1 <Process Name> : Optional Label 2 PROCESS : Keyword 3 sensitivity list : Signals inside it when make an event, the process trigger 4 process declaration 5 Begin : Keyword 6 Sequential statements 7 End : Process Suspend Session Three 10
11. 11. Connecting ProcessesProcesses and other concurrent operations are seen to take place at the same point in • Click to edit Master text stylesdiscrete simulation time – Second levela suspended process is activated when any of signal of sensitivity list changes. • Third levelIf we have multiple process and all is activated then all statement is each process isexecuted sequentially . – Fourth level » Fifth levelall process in any architecture are executed concurrently with each other. a a b Process c b 1 Process c 2 Process 3 Session Three 11
12. 12. Transactions and Events• Click to edit Master text stylesProcess (enable,A,B)A B Cbegin – Second level if enable =„1„ then 0 1 0 C <= A AND B ; 1 0 0 • end if; Third level 1 1 1end process – Fourth level ; » Fifth level-Transaction occurs once a statement is read and executed during if condition -only one branch is transacted ‘the true conditionstatements.-The current value of A,B is read and the process is begun . C <= A AND B ; causes a transaction-The value in C is updated when the process suspend.-If the value of C is changed as a result of this transaction, an event occurs onthis signal. Transaction occurs when the process suspend on read and executed signals Event occurs on signal when the value changes on a transacted signal Session Three 12
13. 13. Transactions and Events• Click to edit Master text stylesAll signal assignment cause a transaction to be scheduled, but not everytransaction will result in an event on the target signal.Note – Second level • Third levelOnly an event on a given signal will cause a process to trigger if that signal isincluded in its sensitivity list. – Fourth level1-Signal A =0 » Fifth level2-Signal B changes to 03-process triggers on signal B event A 04-Expression reevaluated5-Transaction scheduled logic 0 on C B6-Process suspend C 07-Tranasction applied to C8-Value of C does not changed Transaction applied at signal ‘C’9-No event on C only Transaction Session Three 13
14. 14. Example 13Find values of A,D and B after run simulation • Click to edit Master text stylesSignalProcess (A,B) Valuebegin Stored – Second level A <= B + C ; E 3 D <= B + E ; B <= F • Third level + G ; C 2 –end process ; Fourth level F 4 » Fifth level B 1 Signal After first time After G 5 this Process Process Trigger for the Suspend first time A 3 11 D 4 12 B 9 9 Session Three 14
15. 15. Concurrent Statements [3-When Else]• Click <= edit Masterwhen <condition><target> to <expression> text styles else – Second<expression> level <expression> when <condition> else when <condition> • Third…level else <expression> ; – Fourth level » Fifth level– LHS can be an internal signal or an output port– RHS is an expression that operates on internal signal and/or input ports when the branch condition is true– Last “else” branch covers all missing conditions Session Three 15
16. 16. Example 144 x 1 Multiplexer • Click to edit Master text styles – Second level A B FArchitecture behave of mux_when isBegin • Third level C F <= – Fourth level = "00" else a when sel D b when sel = "01" else » Fifth level c when sel = "10" else d when sel = "11" else „Z‟; Sel-- This is one statement withsemicolon at the end onlyEnd behave ; Session Three 16
17. 17. Concurrent Statements [4-With Select]• Click to edit Master text stylesWith <select_signal> select – Second level<expression> <target> <= <expression> when <value>, when <value>, • Third level …. < expression> when others; – Fourth level » Fifth level– <select_signal> can be an internal signal or an input port– <target> can be an internal signal or an output port– <value> constants representing one of possible <select_signal> values.– “When others” is a must if not all values of <select_signal> are covered Session Three 17
18. 18. Example 154 x 1 Multiplexer • Click to edit Master text styles – Second level A B F • Third levelArchitecture behave of mux_with is CBegin With – Fourth level sel select D F »<= a when "00", Fifth level b when "01", c when "10", Sel d when "10", „Z‟ when others; -- When Others needed to cover missing “sel” valuesEnd behave ; Session Three 18
19. 19. Question !! • Click to edit Master text stylesWhat is the result in the two casesProcess (B,C)begin A <= B ; A <= B ; – Second level A <= C ; A <= C ;end • Third levelAre the Same ?!! – Fourth levelA <= D; B <= C;B <= C; » Fifth level A <= D;Are the Same ?!!Process (clk) A <= B;begin C <= A; A <= B; C <= A;endWhich SWAP ?!!Process (B,A) A <= B;begin A <= B ; B <= A; B <= A ;end Session Three 19
20. 20. Question !! • Click to edit Master text stylesWhat is the result in the two casesProcess (B,C) 1 :A=C stbegin A <= B ; A <= B ; – Second level A <= C ; A <= C ; 2nd : Conflictend • Third levelAre the Same ?!! – Fourth levelA <= D; B <= C;B <= C; » Fifth level A <= D; The SameAre the Same ?!!Process (clk) A <= B;begin Inside Process connected C <= A; A <= B; as registers A = last B C <= A; C = last Aend Outside Process wiring B=CWhich SWAP ?!!Process (B,A) A <= B;begin A <= B ; B <= A; The First B <= A ;end Session Three 20
21. 21. Lab 03• Click to edit Master text stylesTitle:Simulate 2X4 Decoder or 4X2 Encoder Using When-else and With-Select-When – Second levelMake the Code enabled by input ‘ENABLE’ • Third levelGoal: – Fourth level  Main Lab on Concurrent Statements » Fifth level Session Three 21
22. 22. Lab 03 • Click to edit Master text stylesWHEN-ELSE vs WITH SELECT WHEN – Second levelWith <select_signal> select • Third level <target> <= <expression> when <value>, <expression> when <value>, …. – Fourth level < expression> when others; » Fifth level------------------------------------------------------------------------------------<target> <= <expression> when <condition> else <expression> when <condition> else <expression> when <condition> … else <expression> ; Session Three 22
23. 23. Lab 03 • Click to edit Master text styles2X4 DecoderArchitecture behave of decoder2x4 is – Second levelBegin F <= "0001" when a = "00" else • Third "0010" when a = "01" else level "0100" when a = "10" else – Fourth level “1000" when a = "11" else “ZZZZ"; » Fifth levelEnd behave ;---------------------------------------------Architecture behave of decoder2x4 isBegin With a select F <= "0001" when "00", "0010" when "01", “0100" when "10", “1000" when "11", “ZZZZ" when others;End behave ; Session Three 23
24. 24. Lab 03 • Click to edit Master text styles4X2 EncoderArchitecture behave of encoder4x2 isBegin – Second “00" when F <= level a = “1000" else "01" when a = “0100" else • Third level "10" when a = “0010" else – Fourth level "11" when a = “0001" else “ZZ"; level » FifthEnd behave ;---------------------------------------------Architecture behave of encoder4x2 isBegin with A select F <= "00" when “1000", "01" when "0100", "10" when “0010", "11" when “0001", “ZZ" when others;End behave ; Session Three 24
25. 25. Break • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth levelBe ready for the 2 nd part of this session15 minutes started from 4:59 AM 25
26. 26. Outline• Click to edit Master text styles Statement Concurrent Statements 1-Assign – Second level 2-Process 3-When-else • Third level 4-With-select – Fourth level Data Objects » Fifth level 1-Signals 2-Variables 3-Constants Session Three 26
27. 27. Data Objects• Click to edit Master text styles-Data Objects are the Value holders – Second level-VHDL offers different data objects: • Third level1-Signals – Fourth level Used to model connections » Fifth level Signals can be: - External Signals - Internal Signals2-Variables Used for computations3-Constants Used to store values that can’t be changed during synthesis or simulation time Session Three 27
28. 28. Data Objects [1- Signals]• Click to edit Master text stylesSignals Used to model connections, signals can be divided into two main types : – Second level External Signals (Ports) • ThirdUsedvaluesinterface for the Entitybetween its internal units. level an in and out the circuit, to the outside world pass as – Fourth level Declared in Entity All PORTS of an ENTITY are signals by default » Fifth level Internal Signals Used inside the Architecture to connect different logic parts Declared in Architecture Represents circuit interconnects (wires) Session Three 28
29. 29. Data Objects [1- Signals]External Signal declaration• Click to edit Master text styles entity <entity_name> is – Second level port ( <port_name> : <mode> <type>; Example ENTITY AND_GATE IS port ( a,b : in BIT; • Third level ----- C : out BIT <port_name> : <mode> <type> – Fourth level ); ); END ENTITY AND_GATE ; » Fifth level End <entity_name> ;Internal Signal declaration architecture <arch_name> of <entity_name> is -- architecture declarations Example signal <sig_name> : <sig_type>; SIGNAL control: BIT ; begin SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0); --- End <arch_name> ; Session Three 29
30. 30. Data Objects [1- Signals]• Click to edit Master text stylesAssignment Operator – Second level Assigned using “<=” Non-Blocking AssignmentExample • Third level inp_x <=“0000”; – Fourth level sig_1 <=„1‟;Behavior » Fifth levelUsed in Concurrent or Sequential - Outside a process its value is updated when their signal assignment is executed. - Inside a process its value is updated after the process suspends only last assignment to signal listed inside the process is effective . Session Three 30
31. 31. Example 16Using Signals inside Process • Click to edit Master text styles – Second levelA=1 ,B=1 ,C=1, D=2 ? • Third to 2C changes from 1 level What is the Answer:values of A,B and C ? – Fourth level A=3---------------------------------- » Fifth levelProcess (C,D) B=3Begin A <=2; C=2 B <=A+C; A <=D+1; C <=B+A;End process;---------------------------------- Session Three 31
32. 32. Exercise 02 Find the value of result • Click to edit Master text styles – Second level • Third level Answer:signalsignal1: integer :=1; -- initial valuesignalsignal2: – Fourth :=2; -- initial value integer levelsignalsignal3: integer :=3; -- initial value 6begin » Fifth levelprocess()begin signal1 <= signal2; signal2 <= signal1 + signal3; signal3 <= signal2; RESULT <= signal1 + signal2 + signal3;end process; Session Three 32
33. 33. Exercise 03 All Signals have the uninitialized value ‘U’ Force A = 1 then force A=0 then A=1 • Click to edit Master text styleslibrary IEEE; – Second levelUSE ieee.std_logic_1164.all;entity signal_lab is A 1 0 1 • Third levelport( A: in std_logic );End signal_lab; Z U 0 0Architecture – Fourth of signal_lab is behave level Signal Z,G,F,X : STD_LOGIC; G 0 0 0 » Fifth levelbegin F U 0 0process (A)Begin X U U 0 Z <= A; G <= 1; F <= G; X <= F; G <= 0; Z <= G;end process ;end behave; Session Three 33
34. 34. Exercise 04 All Signals have the uninitialized value ‘U’ Force A = 1 then force A=0 then A=1 • Click to edit Master text styleslibrary IEEE; – Second levelUSE ieee.std_logic_1164.all;entity signal_lab is A 1 0 1 • Third levelport( A: in std_logic );End signal_lab; Z X X XArchitecture – Fourth of signal_lab is behave level Signal Z,G,F,X : STD_LOGIC; G X X X » Fifth levelbegin F U 0 0process (A)Begin X U U 0 Z <= A; G <= 1; Any statement written outside F <= G; process is concurrent statement , X <= F; It execute concurrently with processend process ; G and Z has two values at same time G <= 0; Z <= G;end behave; Session Three 34
35. 35. Data Objects [2- Variables] • Click to edit Master text styles – Second levelVariables are used for computations Represent only local information • Third level Declared inside a process can only be used inside a PROCESS (in sequential code). – Fourth levelVariable declaration » Fifth levelarchitecture behave of MPU isbegin process() variable x, y : std_logic ; variable intbus : std_logic_vector(7 downto 0); begin . . . end process ; . .end behave; Session Three 35
36. 36. Data Objects [2- Variables]• Click to edit Master text stylesAssignment Operator Assigned using “:=” – Second level Blocking AssignmentExample • Third level var_x :=“0000”; – Fourth level var_1 :=„1‟;Behavior » Fifth level its value can not be passed out directly its update is immediate, so the new value is used in the next line of code. As long as signal and variable have same type they can be assign to each other . Session Three 36
37. 37. Example 17Using Variables inside the process • Click to edit Master text styles – Second levelA=1 ,B=1 ,C=1, D=2 ?C changes from 1 to 2 • Third levelWhat is the values of A,B and C ? Answer: – Fourth level A=3----------------------------------Process (C,D) » Fifth level …. B=4Begin C=7 A :=2; B :=A+C; A :=D+1; C :=B+A;End process;---------------------------------- Session Three 37
38. 38. Exercise 05 • Click to edit Master text stylesFind Result value – Second levelbegin • Third level Answer:process() – Fourth levelvariable variable1: integer :=1; -- initial value 12variable variable2: integer :=2; -- initial value » Fifth levelvariable variable3: integer :=3; -- initial valuebegin variable1 := variable2; variable2 := variable1 + variable3; variable3 := variable2; RESULT := variable1 + variable2 +variable3;end process; Session Three 38
39. 39. Exercise 06 Force A = "0001" and find values of signals • Force A = to edit Master text styles-- Click “0001" – Second levellibrary IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all; A 0001 • Third levelentity signal_lab isport( G 0010 – Fourth level A : in std_logic_vector(3 downto 0) );End signal_lab; » Fifth level F 0011 X 0101Architecture behave of signal_lab isbegin Z 0111 process (A) Variable Z,G,F,X : std_logic_vector(2 downto 0); Begin G := A + A; F := G + A; X := G + F; Z := X + F; end process ;end behave; Session Three 39
40. 40. Data Objects [3-Constants] • Click to edit Master text stylesA constant can have a single value of a given type and cannot be changed during thesimulation. – Second levelConstant Declaration • Third level – constant Fourth level : <data_type> := <con_value>; <con_name> » Fifth levelConstants can be declared at the start of an architecture and can then be used anywherewithin the architecture.Constants declared within a process can only be used inside this Process.Example CONSTANT set_bit : BIT := 1; Session Three 40
41. 41. Data Objects [Initialization] • make Initialization to values to start withtext styles of ‘U’ on the simulationwe Click to edit Master a certain value instead – Second levelwhen we declare the variable or the Signal using := • Third level signal sigbus – Fourth : std_logic_vector(7 downto 0) := "01011110"; level variable z » Fifth std_logic : level := 1; variable varbus : std_logic_vector(3 downto 0) := "0001"; Session Three 41
42. 42. Signal vs Variable • Click to edit Master text styles Variables Signals – Second level Architecture DeclarationDeclaration Internal : Inside Inside Process Declaration • Third level : External Inside Port entity – Fourth levelAssignment Non-Blocking Assign <= Blocking Assign :=Initialization » Fifth level := :=Update After the process suspend ImmediatelyScope Seen by the whole code Local onside process Can be used in either type of Can only be used inside code, concurrent or sequential. a sequential codeUTILITY Represents circuit interconnects Represents local information (wires) NOT APPEAR on SIMULATION Session Three 42
43. 43. Object Scope• Clickarchitecture, local signals top level (entity) to edit Masterdeclared styles-Ports are signals and declared at the-Within the are text-Within the process, local variables can be declared – Second level • Third level ENTITY ARCHITECTURE – ……. Fourth level ……. » Fifth level PROCESS ……. variables Signals IN PORTS OUT PORTS Session Three 43
44. 44. Exercise 07Calculate the values of var1, sig1& Q• Click to edit Master text styles – Second levelprocess (a,b) variable var1: integer;begin • Third level var1 := a + b; sig1 <= var1; Q <= sig1; – Fourth levelend process; » Fifth level Var1 sig1 Q Intial 3 4 6 values A=2 5 5 4 B=3 A=5 7 7 5 B=2 Session Three 44
45. 45. Start Notes [Synthesis Notes]• Click to edit Master text styles Example of Combinational Process 4X1 MUX – Second levelCombinational Process process (a,b,c,d,sel) • Third level beginProcess is combinational if Case sel isall the signals –inFourth level When "00" => yourprocess are in »theFifth level f <= a;sensitivity list . Process that When "01" =>translate a combinational f <= b;logic is for sure doesn’t When "10" => f <= c;include any clock signals. When "11" => f <= d; when others => f <= „Z‟; End case; End process; Session Three 45
46. 46. Start Notes [Synthesis Notes]• Click to edit Master text styles Initialization – Second levelSignals Initialization If reset = 1 then • Third level sig_1 <= 0 ;Signals inside your design sig_2 <= 00000; – valuesshould have initial Fourth level sig_3 <= 10101010;Synthesis tools ignore » Fifth level ris…… <= elsif out_1 00initial values specified for a …..variable or a signal in its …declaration. The best wayfor initialization is toinitialize the signals whenthe reset signal is active. Session Three 46
47. 47. Start Notes [Simulation Notes]• Click to edit Master text of discrete simulation time: - At any single point styles – Second levelModeling Concurrency (1) All processes execute until they suspend (2) Signals are updated • Third level (3) Events on signals cause more processes to resume execution This is referred to as a delta cycleA VHDL simulator is eventdriven. More – Fourth level eventsoccurs, more time » Fifth leveltransaction is scheduled at its appropriate discrete time your Eachsimulator runs. The event Discrete time advances only when no more transactions arescheduler is the heart of scheduled at the current timethe HDL behavioralenvironment. Simulation discrete time step Delta cycles in-between Concurrent Operations Session Three 47
48. 48. Summary• Click to edit Master text styles- VHDL is a Hardware Description Language so the default statements in VHDL are – Second level those who are executed in parallel • Third level- External Signals describe interface while Internal Signals describe internal wiring .- Variables describe internal calculations inside a process. – Fourth level » Fifth level Examples Exercises Labs 13-17 2-7 2-3 Session Three 48
49. 49. Time for Your Questions• Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Session Three 49
50. 50. Download Session 02 Files• Click to edit Master text stylesRead Session- 3 Examples carefully to be ready for the next session’s LABs –Lab 02 www.startgroup.weebly.com/vhdl-examples.html Second level • Third level Lab 03 – www.startgroup.weebly.com/vhdl-examples.html Fourth level » Fifth level Session Three 50
51. 51. Take Your Notes Print the slides and take your notes here---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ – Second level------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ • Third level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- – Fourth level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- » Fifth level----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
52. 52. See You Next Session .. Don’t miss• Click to edit Master text styles Thank – Second level • Third level – Fourth level You » Fifth level