Session 03 v.3

• Click to edit Master text styles
– Second level
• Third level
– Fourthg i t a l D e s i g n u s i n g V H D L
D i level
Session Three
» Fifth level

Introduced by

Cairo-Egypt

Version 03 – June 2012 1

about Start Group

Mahmoud Abdellatif
– Second level
Alaa Salah Shehata
Mohamed level
• Third Salah
Mohamed Talaat
– Fourth level
» Fifth level
start.courses@gmail.com www.slideshare.net/StartGroup

www.facebook.com/groups/start.group

www.startgroup.weebly.com Start.courses@gmail.com

+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011
+ 02 0128-0090250 A.S

Session Three 2

Lab 02

Title:
Simulation of a Register on Modelsim
– Second level
Goal:
•
 Third level synchronous sequential circuits
Be familiar with
 Solution of last session Assignment
– Fourth level
» Fifth level

Session Three 3

Lab 02

Register
Library ieee; D
Q
– Second level
use ieee.std_logic_1164.all;
Entity d_ff is Reset Register
Q’
Port( d, clk, rst : in std_logic;
• Third level
Q,Q_inv : out std_logic);
end entity;
– Fourth level
Architecture behav of d_ff is clk
Signal Q_sig : std_logic;
» Fifth level
Begin
process(clk, rst)
begin
If (rst = '1') then
Q_sig <= '0';
elsif rising_edge(clk) then
Q_sig <= d;
end if;
end process;
Q <= Q_sig;
Q_inv <= not Q_sig;
end behav;
Session Three 4

Outline

• Click to edit Master text styles Statement
– Second level
• Third level
Concurrent Statements
1-Assign
2-Process
3-When-else
4-With-select
3
– Fourth level
Data Objects
» Fifth level 1-Signals
2-Variables
3-Constants

Session Three 5

Outline

1-Assign
– Second level 2-Process
3-When-else
• Third level 4-With-select
– Fourth level
Data Objects
2-Variables
3-Constants

Session Three 6

VHDL Statements

• Click to edit Master Assignment
text styles
– Second level
Concurrent
Process

• Third level When-Else
– Fourth level
With-Select
Statements » Fifth level
IF

CASE
Sequential
FOR

WAIT

Session Three 7

Concurrency Concept

We can consider any system to be consisted of many blocks each has a specific
function and work together concurrently (in parallel) to form the whole
function.
– Second level
As VHDL is a Hardware Description Language so the default statements in VHDL
• Third level
are those who are executed in parallel.
– are called Concurrent statements.
These statementsFourth level
» Fifth level

Session Three 8

Concurrent Statements [1-Assign <=]

- Assignments relating outputs to inputs
- Non Blocking Assignment <= is used
- Assign statements can be written in any order.
– Second level
In this Example, the value of x depends on a AND b, whenever a/b changes x will
• Third level
change accordingly
– Fourth level
Similarly the value of yFifthalways change whenever c/d changes
» will level
It might happen that the value of x changes at the same time the value of y changes
-> Both changes happen concurrently
a
x
begin
x <= a AND b;
b
y <= c AND d; e
c
e <= x AND y;
end rtl;
y
d
Session Three 9

Concurrent Statements [2-Process]

Process allows writing sequential statements within concurrent environment

– declaration
Process Second level
2
1 • Name> : PROCESS (sensitivity list) 3
<Process Third level
-- process declaration; 4
5 Begin
– Fourth level
» Fifth level
-- sequential statements ; 6
7 End PROCESS <Process Name> ;

1 <Process Name> : Optional Label
2 PROCESS : Keyword
3 sensitivity list :
Signals inside it when make an event, the process trigger
4 process declaration
5 Begin : Keyword
6 Sequential statements
7 End : Process Suspend
Session Three 10

Connecting Processes

Processes and other concurrent operations are seen to take place at the same point in
discrete simulation time

– Second level
a suspended process is activated when any of signal of sensitivity list changes.

• Third level
If we have multiple process and all is activated then all statement is each process is
executed sequentially .
– Fourth level
» Fifth level
all process in any architecture are executed concurrently with each other.
a a
b
Process

c b 1
Process
c 2

Process
3
Session Three 11

Transactions and Events

Process (enable,A,B)A B C
begin
– Second level
if enable =„1„ then
0 1 0
C <= A AND B ; 1 0 0
•
end if; Third level 1 1 1
end process – Fourth level
;

» Fifth level
-Transaction occurs once a statement is read and executed
during if condition -only one branch is transacted ‘the true condition
statements.
-The current value of A,B is read and the process is begun .
C <= A AND B ; causes a transaction
-The value in C is updated when the process suspend.
-If the value of C is changed as a result of this transaction, an event occurs on
this signal.
Transaction occurs when the process suspend on read and executed signals
Event occurs on signal when the value changes on a transacted signal
Session Three 12

Transactions and Events

All signal assignment cause a transaction to be scheduled, but not every
transaction will result in an event on the target signal.

Note – Second level
• Third level
Only an event on a given signal will cause a process to trigger if that signal is
included in its sensitivity list.
– Fourth level
1-Signal A =0 » Fifth level
2-Signal B changes to 0
3-process triggers on signal B event A 0
4-Expression reevaluated
5-Transaction scheduled logic 0 on C
B
6-Process suspend
C 0
7-Tranasction applied to C
8-Value of C does not changed Transaction applied at signal ‘C’
9-No event on C only Transaction

Session Three 13

Example 13

Find values of A,D and B after run simulation
• Click to edit Master text stylesSignal
Process (A,B) Value
begin Stored
– Second level
A <= B + C ;
E 3
D <= B + E ;
B <= F • Third level
+ G ; C 2
–
end process ; Fourth level
F 4
» Fifth level B 1
Signal After first time After G 5
this Process Process
Trigger for the Suspend
first time
A 3 11
D 4 12
B 9 9

Session Three 14

Concurrent Statements [3-When Else]

• Click <= edit Masterwhen <condition>
<target>
to <expression> text styles else
– Second<expression>
level
<expression>
when <condition> else
when <condition>
• Third…level else
<expression> ;
– Fourth level
» Fifth level
– LHS can be an internal signal or an output port
– RHS is an expression that operates on internal signal and/or input ports when
the branch condition is true
– Last “else” branch covers all missing conditions

Session Three 15

Example 14

4 x 1 Multiplexer
– Second level A
B F
Architecture behave of mux_when is
Begin
• Third level C
F <= – Fourth level = "00" else
a when sel D
b when sel = "01" else
» Fifth level
c when sel = "10" else
d when sel = "11" else
„Z‟;
Sel
-- This is one statement with
semicolon at the end only
End behave ;

Session Three 16

Concurrent Statements [4-With Select]

With <select_signal> select
– Second level<expression>
<target> <=
<expression>
when <value>,
when <value>,
• Third level ….
< expression> when others;
– Fourth level
» Fifth level

– <select_signal> can be an internal signal or an input port
– <target> can be an internal signal or an output port
– <value> constants representing one of possible <select_signal> values.
– “When others” is a must if not all values of <select_signal> are covered

Session Three 17

Example 15

4 x 1 Multiplexer
– Second level A
B F
• Third level
Architecture behave of mux_with is C
Begin
With – Fourth level
sel select D
F »<= a when "00",
Fifth level
b when "01",
c when "10", Sel
d when "10",
„Z‟ when others;
-- When Others needed to cover
missing “sel” values
End behave ;

Session Three 18

Question !!

What is the result in the two cases
Process (B,C)
begin A <= B ; A <= B ;
– Second level
A <= C ; A <= C ;
end
• Third level
Are the Same ?!!
– Fourth level
A <= D; B <= C;
B <= C; » Fifth level
A <= D;
Are the Same ?!!
Process (clk) A <= B;
begin C <= A;
A <= B;
C <= A;
end
Which SWAP ?!!
Process (B,A) A <= B;
begin A <= B ; B <= A;
B <= A ;
end
Session Three 19

Question !!

What is the result in the two cases
Process (B,C) 1 :A=C st
begin A <= B ; A <= B ;
– Second level
A <= C ; A <= C ;
2nd : Conflict
end
• Third level
Are the Same ?!!
– Fourth level
A <= D; B <= C;
B <= C; » Fifth level
A <= D; The Same

Are the Same ?!!
Process (clk) A <= B;
begin Inside Process connected
C <= A;
A <= B; as registers A = last B
C <= A; C = last A
end Outside Process wiring B=C
Which SWAP ?!!
Process (B,A) A <= B;
begin A <= B ; B <= A; The First
B <= A ;
end
Session Three 20

Lab 03

Title:
Simulate 2X4 Decoder or 4X2 Encoder Using When-else and With-Select-When
– Second level
Make the Code enabled by input ‘ENABLE’
• Third level
Goal:
– Fourth level
 Main Lab on Concurrent Statements
» Fifth level

Session Three 21

Lab 03

WHEN-ELSE vs WITH SELECT WHEN

– Second level
With <select_signal> select
• Third level
<target> <= <expression> when <value>,
<expression> when <value>,
…. – Fourth level
< expression> when others;
» Fifth level
------------------------------------------------------------------------------------

<target> <= <expression> when <condition>
else <expression> when <condition>
else <expression> when <condition>
…
else <expression> ;

Session Three 22

Lab 03

2X4 Decoder
Architecture behave of decoder2x4 is
– Second level
Begin
F <= "0001" when a = "00" else
• Third "0010" when a = "01" else
level
"0100" when a = "10" else
– Fourth level
“1000" when a = "11" else
“ZZZZ";
» Fifth level
End behave ;
---------------------------------------------
Architecture behave of decoder2x4 is
Begin
With a select
F <= "0001" when "00",
"0010" when "01",
“0100" when "10",
“1000" when "11",
“ZZZZ" when others;
End behave ;
Session Three 23

Lab 03

4X2 Encoder
Architecture behave of encoder4x2 is
Begin
– Second “00" when
F <= level a = “1000" else
"01" when a = “0100" else
• Third level
"10" when a = “0010" else
– Fourth level
"11" when a = “0001" else
“ZZ"; level
» Fifth
End behave ;
---------------------------------------------
Architecture behave of encoder4x2 is
Begin
with A select
F <= "00" when “1000",
"01" when "0100",
"10" when “0010",
"11" when “0001",
“ZZ" when others;
End behave ;
Session Three 24

Break
– Second level
• Third level
– Fourth level
» Fifth level
Be ready for the 2 nd part of this session

15 minutes started from
4:59 AM 25

Outline

1-Assign
– Second level 2-Process
3-When-else
• Third level 4-With-select
– Fourth level
Data Objects
2-Variables
3-Constants

Session Three 26

Data Objects

-Data Objects are the Value holders
– Second level
-VHDL offers different data objects:
• Third level
1-Signals
– Fourth level
Used to model connections
» Fifth level
Signals can be:
- External Signals
- Internal Signals

2-Variables
Used for computations

3-Constants
Used to store values that can’t be changed during synthesis or simulation time

Session Three 27

Data Objects [1- Signals]

Signals Used to model connections, signals can be divided into two main types :

– Second level
External Signals (Ports)
• ThirdUsedvaluesinterface for the Entitybetween its internal units.
level an in and out the circuit, to the outside world
pass
as

– Fourth level
Declared in Entity
All PORTS of an ENTITY are signals by default
» Fifth level
Internal Signals
Used inside the Architecture to connect different logic parts
Declared in Architecture
Represents circuit interconnects (wires)

Session Three 28


External Signal declaration
entity <entity_name> is
– Second level
port (
<port_name> : <mode> <type>;
Example
ENTITY AND_GATE IS
port ( a,b : in BIT;
• Third level
----- C : out BIT
<port_name> : <mode> <type>
– Fourth level );
); END ENTITY AND_GATE ;
» Fifth level
End <entity_name> ;

Internal Signal declaration
architecture <arch_name> of
<entity_name> is
-- architecture declarations Example
signal <sig_name> : <sig_type>;
SIGNAL control: BIT ;
begin
SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0);
---
End <arch_name> ;

Session Three 29


Assignment Operator
– Second level
Assigned using “<=”
Non-Blocking Assignment
Example
• Third level
inp_x <=“0000”;
– Fourth level
sig_1 <=„1‟;
Behavior
» Fifth level
Used in Concurrent or Sequential
- Outside a process
its value is updated when their signal assignment is executed.
- Inside a process
its value is updated after the process suspends
only last assignment to signal listed inside the process is effective .

Session Three 30

Example 16

Using Signals inside Process
– Second level
A=1 ,B=1 ,C=1, D=2 ?
• Third to 2
C changes from 1 level What is the Answer:
values of A,B and C ?
– Fourth level A=3
----------------------------------
» Fifth level
Process (C,D) B=3
Begin
A <=2; C=2
B <=A+C;
A <=D+1;
C <=B+A;
End process;
----------------------------------

Session Three 31

Exercise 02

Find the value of result
– Second level
• Third level Answer:
signalsignal1: integer :=1; -- initial value
signalsignal2: – Fourth :=2; -- initial value
integer level
signalsignal3: integer :=3; -- initial value
6
begin » Fifth level
process()
begin
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;

Session Three 32

Exercise 03

All Signals have the uninitialized value ‘U’ Force A = '1' then force A='0' then A='1'
library IEEE;
– Second level
USE ieee.std_logic_1164.all;
entity signal_lab is
A 1 0 1
• Third level
port( A: in std_logic );
End signal_lab; Z U 0 0
Architecture – Fourth of signal_lab is
behave level
Signal Z,G,F,X : STD_LOGIC; G 0 0 0
» Fifth level
begin F U 0 0
process (A)
Begin X U U 0
Z <= A;
G <= '1';
F <= G;
X <= F;
G <= '0';
Z <= G;
end process ;
end behave;
Session Three 33

Exercise 04

All Signals have the uninitialized value ‘U’ Force A = '1' then force A='0' then A='1'
library IEEE;
– Second level
A 1 0 1
• Third level
port( A: in std_logic );
End signal_lab; Z X X X
Architecture – Fourth of signal_lab is
behave level
Signal Z,G,F,X : STD_LOGIC; G X X X
» Fifth level
begin F U 0 0
process (A)
Begin X U U 0
Z <= A;
G <= '1'; Any statement written outside
F <= G; process is concurrent statement ,
X <= F; It execute concurrently with process
end process ; G and Z has two values at same time
G <= '0';
Z <= G;
end behave;
Session Three 34

Data Objects [2- Variables]

– Second level
Variables are used for computations
Represent only local information
• Third level
Declared inside a process
can only be used inside a PROCESS (in sequential code).
– Fourth level
Variable declaration » Fifth level
architecture behave of MPU is
begin
process()
variable x, y : std_logic ;
variable intbus : std_logic_vector(7 downto 0);
begin
. . .
end process ;
. .
end behave;

Session Three 35

Data Objects [2- Variables]

Assignment Operator
Assigned using “:=”
– Second level
Blocking Assignment

Example
• Third level
var_x :=“0000”;
– Fourth level
var_1 :=„1‟;
Behavior
» Fifth level
its value can not be passed out directly
its update is immediate, so the new value is used in the next line of code.
As long as signal and variable have same type they can be assign to each other .

Session Three 36

Example 17

Using Variables inside the process
– Second level
A=1 ,B=1 ,C=1, D=2 ?
C changes from 1 to 2
• Third level
What is the values of A,B and C ? Answer:
– Fourth level A=3
----------------------------------
Process (C,D) » Fifth level
….
B=4
Begin C=7
A :=2;
B :=A+C;
A :=D+1;
C :=B+A;
End process;
----------------------------------

Session Three 37

Exercise 05

Find Result value

– Second level
begin
• Third level Answer:
process()
– Fourth level
variable variable1: integer :=1; -- initial value 12
variable variable2: integer :=2; -- initial value
» Fifth level
variable variable3: integer :=3; -- initial value

begin
variable1 := variable2;
variable2 := variable1 + variable3;
variable3 := variable2;
RESULT := variable1 + variable2 +
variable3;
end process;

Session Three 38

Exercise 06

Force A = "0001" and find values of signals
• Force A = to edit Master text styles
--
Click “0001"
– Second level
library IEEE;
USE ieee.std_logic_unsigned.all; A 0001
• Third level
port( G 0010
– Fourth level
A : in std_logic_vector(3 downto 0) );
End signal_lab; » Fifth level F 0011
X 0101
Architecture behave of signal_lab is
begin Z 0111
process (A)
Variable Z,G,F,X : std_logic_vector(2 downto 0);
Begin
G := A + A;
F := G + A;
X := G + F;
Z := X + F;
end process ;
end behave;
Session Three 39

Data Objects [3-Constants]

A constant can have a single value of a given type and cannot be changed during the
simulation.
– Second level
Constant Declaration
• Third level
–
constant Fourth level : <data_type> := <con_value>;
<con_name>

» Fifth level
Constants can be declared at the start of an architecture and can then be used anywhere
within the architecture.

Constants declared within a process can only be used inside this Process.

Example

CONSTANT set_bit : BIT := '1';

Session Three 40

Data Objects [Initialization]

• make Initialization to values to start withtext styles of ‘U’ on the simulation
we
Click to edit Master a certain value instead
– Second level
when we declare the variable or the Signal using :=

• Third level
signal sigbus
– Fourth : std_logic_vector(7 downto 0) := "01011110";
level
variable z » Fifth std_logic
: level := '1';

variable varbus : std_logic_vector(3 downto 0) := "0001";

Session Three 41

Signal vs Variable

• Click to edit Master text styles Variables
Signals

– Second level Architecture Declaration
Declaration Internal :
Inside
Inside Process Declaration

• Third level :
External
Inside Port entity
– Fourth level
Assignment Non-Blocking Assign <= Blocking Assign :=
Initialization
» Fifth level
:= :=
Update After the process suspend Immediately
Scope Seen by the whole code Local onside process

Can be used in either type of Can only be used inside
code, concurrent or sequential. a sequential code
UTILITY Represents circuit interconnects Represents local information
(wires) NOT APPEAR on SIMULATION

Session Three 42

Object Scope

• Clickarchitecture, local signals top level (entity)
to edit Masterdeclared styles
-Ports are signals and declared at the
-Within the are
text
-Within the process, local variables can be declared
– Second level
• Third level
ENTITY
ARCHITECTURE
–
……. Fourth level
…….
» Fifth level PROCESS
…….

variables

Signals

IN PORTS OUT PORTS

Session Three 43

Exercise 07

Calculate the values of var1, sig1& Q
– Second level
process (a,b)
variable var1: integer;
begin
• Third level
var1 := a + b;
sig1 <= var1;
Q <= sig1;
– Fourth level
end process; » Fifth level

Var1 sig1 Q
Intial 3 4 6
values
A=2 5 5 4
B=3
A=5 7 7 5
B=2

Session Three 44

Start Notes [Synthesis Notes]

Example of Combinational Process 4X1 MUX
– Second level
Combinational Process
process (a,b,c,d,sel)
• Third level begin
Process is combinational if Case sel is
all the signals –inFourth level When "00" =>
your
process are in »theFifth level f <= a;
sensitivity list . Process that When "01" =>
translate a combinational f <= b;
logic is for sure doesn’t When "10" =>
f <= c;
include any clock signals.
When "11" =>
f <= d;
when others =>
f <= „Z‟;
End case;
End process;

Session Three 45

Start Notes [Synthesis Notes]

Initialization
– Second level
Signals Initialization If reset = 1 then
• Third level sig_1 <= 0 ;
Signals inside your design sig_2 <= 00000;
– values
should have initial Fourth level sig_3 <= 10101010;
Synthesis tools ignore » Fifth level ris…… <=
elsif
out_1 00
initial values specified for a
…..
variable or a signal in its
…
declaration. The best way
for initialization is to
initialize the signals when
the reset signal is active.

Session Three 46

Start Notes [Simulation Notes]

• Click to edit Master text of discrete simulation time:
- At any single point
styles
– Second level
Modeling Concurrency
(1) All processes execute until they suspend
(2) Signals are updated
• Third level (3) Events on signals cause more processes to resume execution
This is referred to as a delta cycle
A VHDL simulator is event
driven. More – Fourth level
events
occurs, more time » Fifth leveltransaction is scheduled at its appropriate discrete time
your Each
simulator runs. The event Discrete time advances only when no more transactions are
scheduler is the heart of scheduled at the current time
the HDL behavioral
environment. Simulation discrete time step
Delta cycles in-between

Concurrent Operations

Session Three 47

Summary

- VHDL is a Hardware Description Language so the default statements in VHDL are
– Second level
those who are executed in parallel
• Third level
- External Signals describe interface while Internal Signals describe internal wiring .
- Variables describe internal calculations inside a process.
– Fourth level
» Fifth level

Examples Exercises Labs
13-17 2-7 2-3

Session Three 48

Time for Your Questions

– Second level
• Third level
– Fourth level
» Fifth level

Session Three 49

Download Session 02 Files

Read Session- 3 Examples carefully to be ready for the next session’s LABs

–Lab 02 www.startgroup.weebly.com/vhdl-examples.html
Second level
• Third level
Lab 03 – www.startgroup.weebly.com/vhdl-examples.html
Fourth level
» Fifth level

Session Three 50

Take Your Notes
Print the slides and take your notes here
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See You Next Session .. Don’t miss


Thank
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• Third level
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You
» Fifth level

Session 03 v.3

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