Rob Pike discusses Plan 9, an operating system developed at Bell Labs as the successor to UNIX. Some key points of Plan 9 include its use of /proc instead of /dev for I/O, its distributed file system design with everything treated as a file, and its emphasis on concurrency through lightweight processes and message passing. Plan 9 aims to improve on UNIX with a more unified and simplified design.
The document discusses the Lua virtual machine (LuaVM) bytecode format and instructions. It shows an example Lua function written in bytecode format, with each instruction taking up one bytecode. The bytecode format uses registers to reference values on the stack and constants to reference values in the constant table. Common Lua operations like variable assignment and table indexing can be represented in a single bytecode instruction this way.
About GStreamer 1.0 application development for beginnersShota TAMURA
Written in Japanese
This slides that was made for me to speak.
so, description in slides may not enough.
Agenda
- Overview
- Data structure
- The basic steps of gstreamer application development
- Tips...
Rob Pike discusses Plan 9, an operating system developed at Bell Labs as the successor to UNIX. Some key points of Plan 9 include its use of /proc instead of /dev for I/O, its distributed file system design with everything treated as a file, and its emphasis on concurrency through lightweight processes and message passing. Plan 9 aims to improve on UNIX with a more unified and simplified design.
The document discusses the Lua virtual machine (LuaVM) bytecode format and instructions. It shows an example Lua function written in bytecode format, with each instruction taking up one bytecode. The bytecode format uses registers to reference values on the stack and constants to reference values in the constant table. Common Lua operations like variable assignment and table indexing can be represented in a single bytecode instruction this way.
About GStreamer 1.0 application development for beginnersShota TAMURA
Written in Japanese
This slides that was made for me to speak.
so, description in slides may not enough.
Agenda
- Overview
- Data structure
- The basic steps of gstreamer application development
- Tips...
The document discusses optimization techniques for deep learning frameworks on Intel CPUs and Fugaku aimed architectures. It introduces oneDNN, a performance library for deep learning operations on Intel CPUs. It discusses issues with C++ implementation, and how just-in-time assembly generation using Xbyak can address these issues by generating optimal code depending on parameters. It also introduces Xbyak_aarch64 for generating optimized code for Fugaku's Scalable Vector Extension instructions.
2022/3/24に開催した「オンプレML基盤 on Kubernetes」の資料です。機械学習モデルの開発者が、よりモデルの開発にのみ集中できるようにすることを目指して開発している「LakeTahoe(レイクタホ)」について紹介します。
https://ml-kubernetes.connpass.com/event/239859/
The document discusses optimization techniques for deep learning frameworks on Intel CPUs and Fugaku aimed architectures. It introduces oneDNN, a performance library for deep learning operations on Intel CPUs. It discusses issues with C++ implementation, and how just-in-time assembly generation using Xbyak can address these issues by generating optimal code depending on parameters. It also introduces Xbyak_aarch64 for generating optimized code for Fugaku's Scalable Vector Extension instructions.
2022/3/24に開催した「オンプレML基盤 on Kubernetes」の資料です。機械学習モデルの開発者が、よりモデルの開発にのみ集中できるようにすることを目指して開発している「LakeTahoe(レイクタホ)」について紹介します。
https://ml-kubernetes.connpass.com/event/239859/
FPGA based 10G Performance Tester for HW OpenFlow SwitchYutaka Yasuda
SDN operators need to measure the performance of OF HW switch on their site. Cause there is 1000 times differences in latency, depends on the specified flow entry. ASIC can forward in several μsecs but the software (CPU) may take msec.
To protect yourself from unexpected performance plunge, monitor your switches healthiness on your site.
A proposal of the OpenFlow controller development support tool Yutaka Yasuda
OpenFlow controller programmer does not have any method to confirm how reflected their code to the flow control, directly and intuitively
“This code, how does work on... which flow?”
“This flow, which code does make it?”
This slides shows the basic design of the mechanism for binding code and flow to see them.
It enables cross referencing logic and flow each other and also enable tracing the flow over switches.
It had been presented at the 16th IOT conference of IPSJ, March 2012.
3. RISC-V : オープンな ISA を求めて
• Berkeley の研究から
• ISA - Instruction Set Architecture
• x86, ARM などは独占的(プロプライエタリ)なビジネスモデル
• オープン・利⽤無料の ISA (32bit, 64bit, 128bit)
• チップやソフトウェアを誰もが⾃由に設計・製作・販売可能
• SoCやチップは MIT, BSD lisence で提供される事が多い(GPL ではない)
• Software もMIT等が多いがベースソフトウェアのライセンスに依存(QEMUはGPL)
https://riscv.org/risc-v-cores/
128bit は事実上予約のみ状態の慎重さ
=誤った予測で将来の負債を作らない
https://riscv.org/software-status/
4. RISC-V ISA (超)概要
• Base Integer ISA
整数レジスタ32本(0番はゼロ固定)
load, store, and/or/xor, add, sub, compare, branch, jump, nop 程度
• And “Optional Instruction-set Extensions”
Standard Extension:⼀般的で互いに衝突しないように設計
Non-Standard Extension:特化+他 Extension との衝突を許容
Embedded向け16本のRV32Eもある
(Standard Extension との conflict も許容)
(浮動⼩数点演算どころか掛け算・割り算もここ)
5. Standard Extensions
Functionality Version
M Integer Multiplication and Division 2.0
A Atomic Instructions 2.0
F Single-Precision Floating-Point 2.0
D Double-Precision Floating-Point 2.0
Q Quad-Precision Floating-Point 2.0
L Decimal Floating-Point 0.0
C Compressed Instructions 2.0
B Bit Manipulation 2.0
J Dynamically Translated Languages 2.0
T Transactional Memory 2.0
P Packed-SIMD Instructions 0.1
V Vector Operations 0.2
N User-Level Interrupts 1.1
source:
The RISC-V Instruction Set Manual, Volume I: User-Level ISA
Document Version 2.2, May 7, 2017
0.0 あたりはまだ内容空⽩
まだまだこれから、的な・・・
Base Integer ISA (I) と MAFD を合わせ
た範囲が、現在のRISC-V tool-chain(コ
ンパイラ等)のデフォルト実装ターゲット
IMAFD で合わせてGとも呼ぶ
ほぉ。トランザクショナルメモリが・・・
F16, F32, F64, F128
どこまで対応するかは実装次第
(Q=F128 はデフォルト実装ターゲットでない)
26. Esperanto Technologies
• 2014, founded by David Ditzel
1980 “The Case for Reduced Instruction Set Computer”,
David Patterson の co-author
Transmeta 覚えてる?
• “building the highest TeraFLOPS per Watt Machine Learning computing system”
• Open Standard ISA + DSE - Domain Specific Engine なアプローチをとる
• 実体は RISC-V による Heterogeneous computing
TSMC 7nm, 2GHz
(⼀つあるいは)少数のパワフルなコアと、⼤量の⼩形 Floating Point ⽤コアの組み合わせ
2018 Oct. RISC-V Day Tokyo での David Ditzel の講演から
27. Maxion(s) + Minions
• Maxion - RISC-V 最⾼のシングルスレッド性能
64K L1, 4M L2, deep pipelines, Out of Order, branch prediction, etc.
wide DRAM interface, Network on die
配置配線(フロアプラン)の画像などいろいろ情報が出てる
• Minion - エネルギー効率重視で 4096 コア(!)を積み込む
In Order, Vector extension of Floating, Tensor instruction
F16, F32, F64, F128 (Quad は RISC-V の実装ターゲットとしては⾮デフォルト)
あまり情報なし(こちらの実装はまだまだ?)
• “All plans subject to change – this is not a product announcement” ステキ(おい)
2018 Oct. RISC-V Day Tokyo での David Ditzel の講演から
28. 汎⽤プロセッサによる AI アプローチ
• “Other companies are proposing special purpose hardware for ML using
proprietary instruction sets.”
• RISC-V なら、、、
ソフトウェアによる leveraging が期待できる
必要な命令セット拡張ができる
(SIMDエンジン - “V” Vector ISA WG の Co-Chair が Esperanto の⼈)
ハードウェア・アクセラレータを追加できる
• “General purpose cores are more desirable (望ましい) than special purpose cores
when minimal performance difference”
2018 Oct. RISC-V Day Tokyo での David Ditzel の講演から
30. source: SiFive presentation
at RISC-V Workshop
in Barselona, 2018 May
https://content.riscv.org/wp-content/uploads/2018/05/09.25-09.55-tate-of-RISC-V-Software-RISC-V-Workshop-at-Barcelona-May-2018-1.pdf
31. Software Status of RISC-V
• Linux Kernel - 4.15 Merged
• Zephyr RTOS - Upstreaming status done
• GCC - Upstream as of 7.1 release
• glibc - Upstream, RISC-V support available starting in 2.27
• binutils - Upstream, RISC-V support available starting in 2.28
• LLVM - MC changes are upstream, assembler and initial codegen patches submitted
• GDB - Bare metal support committed upstream 6 March 2018, was in 8.2 release.
• QEMU - upstream since v2.12, Fedora is able to run on QEMU!
• Imperas Multi Processor Debugger - 商⽤だ!
• Go - bootstrapped and passes tests, still missing cgo-related functionality
https://riscv.org/software-status/
etc., etc. 絶賛対応進⾏中・・・という雰囲気