The document discusses selecting processors to optimize cost-effectiveness for running expensive middleware. It analyzes benchmark results for TPC-C, TPC-H, and SAP on different processors. For TPC-C on Oracle, hyper-threaded Xeons had the best performance per weighted core. For TPC-H, Itanium processors topped benchmarks at a scale of 10,000 but trailed at lower scales. The optimal selection depends on the specific middleware, application, and scale used. Failing to pick the best processor could increase costs by up to 7.4 times.
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This document summarizes the results of experiments measuring the performance impact of cache line contention on large NUMA systems with multiple sockets and cores. The experiments show that:
1) Cache line contention performance degrades smoothly as more cores within a socket participate in contention.
2) Involving cores from multiple sockets in contention causes a huge drop in performance due to increased latency of resolving contention across sockets.
3) Containing cache line contention within as few sockets as possible provides the best performance, with all contention within a single socket performing best.
An Overview of [Linux] Kernel Lock Improvements -- Linuxcon NA 2014Davidlohr Bueso
This document summarizes an overview of kernel lock improvements presented by Davidlohr Bueso and Scott Norton at LinuxConNorth America in August 2014. It discusses the issues of cache line contention in large NUMA systems and how lock contention can cause performance degradation. It presents results of microbenchmarks demonstrating how performance is significantly impacted as more cores and sockets are involved in cache line contention. The document emphasizes that minimizing cache line contention within kernel locking primitives is important for applications to scale well on systems with many sockets and cores.
Ibm and Erb's Presentation Insider's Edition Event . September 2010Erb's Marketing
IBM and Erb's partnership has spanned 20 years. Together we provide world class computing and business technology solutions to growing companies across Iowa and Western Illinois. Here's joint presentation from a recent Erb's customer event - Erb's and IBM review IBM leadership in server and storage technology.
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The document summarizes Oracle database licensing requirements for a server with an Intel Itanium2 1.6GHz dual-core processor with 4 total cores. Oracle licensing is based on the number of processor cores and allows backup and limited failover/clustering. For the server configuration described, the Oracle licensing would be based on 4 CPU cores using the 0.5 multi-core factor.
Ceph Day Beijing - Optimizing Ceph Performance by Leveraging Intel Optane and...Danielle Womboldt
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This document summarizes the results of experiments measuring the performance impact of cache line contention on large NUMA systems with multiple sockets and cores. The experiments show that:
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This document summarizes an overview of kernel lock improvements presented by Davidlohr Bueso and Scott Norton at LinuxConNorth America in August 2014. It discusses the issues of cache line contention in large NUMA systems and how lock contention can cause performance degradation. It presents results of microbenchmarks demonstrating how performance is significantly impacted as more cores and sockets are involved in cache line contention. The document emphasizes that minimizing cache line contention within kernel locking primitives is important for applications to scale well on systems with many sockets and cores.
Ibm and Erb's Presentation Insider's Edition Event . September 2010Erb's Marketing
IBM and Erb's partnership has spanned 20 years. Together we provide world class computing and business technology solutions to growing companies across Iowa and Western Illinois. Here's joint presentation from a recent Erb's customer event - Erb's and IBM review IBM leadership in server and storage technology.
Automated Out-of-Band management with Ansible and RedfishJose De La Rosa
Ansible is an open source automation engine that automates complex IT tasks such as cloud provisioning, application deployment and a wide variety of system administration tasks. It is a one-to-many agentless mechanism where complex deployment tasks can be controlled and monitored from a central control machine.
Redfish is an open industry-standard specification and schema designed for modern and secure management of platform hardware. On Dell EMC PowerEdge servers the Redfish management APIs are available via the integrated Dell Remote Access Controller (iDRAC), which can be used by IT administrators to easily monitor and manage at scale their entire infrastructure using a wide array of clients on devices such as laptops, tablets and smart phones.
Together, Ansible and Redfish can be used by system administrators to fully automate at large scale server monitoring, provisioning and update tasks from one central location, significantly reducing complexity and helping improve the productivity and efficiency of IT administrators.
The document summarizes Oracle database licensing requirements for a server with an Intel Itanium2 1.6GHz dual-core processor with 4 total cores. Oracle licensing is based on the number of processor cores and allows backup and limited failover/clustering. For the server configuration described, the Oracle licensing would be based on 4 CPU cores using the 0.5 multi-core factor.
Ceph Day Beijing - Optimizing Ceph Performance by Leveraging Intel Optane and...Danielle Womboldt
Optimizing Ceph performance by leveraging Intel Optane and 3D NAND TLC SSDs. The document discusses using Intel Optane SSDs as journal/metadata drives and Intel 3D NAND SSDs as data drives in Ceph clusters. It provides examples of configurations and analysis of a 2.8 million IOPS Ceph cluster using this approach. Tuning recommendations are also provided to optimize performance.
Accelerating Cassandra Workloads on Ceph with All-Flash PCIE SSDSCeph Community
This document summarizes the performance of an all-NVMe Ceph cluster using Intel P3700 NVMe SSDs. Key results include achieving over 1.35 million 4K random read IOPS and 171K 4K random write IOPS with sub-millisecond latency. Partitioning the NVMe drives into multiple OSDs improved performance and CPU utilization compared to a single OSD per drive. The cluster also demonstrated over 5GB/s of sequential bandwidth.
Processor Selection for Middleware Price Performance Optimizationdakra137
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Ceph Day Beijing - Optimizing Ceph performance by leveraging Intel Optane and...Ceph Community
The document discusses optimizing Ceph performance by leveraging Intel Optane and 3D NAND TLC SSDs. It provides an overview of using Optane SSDs as journal/metadata drives and 3D NAND SSDs as data drives in Ceph configurations. It then describes achieving 2.8 million IOPS on an all-flash Ceph cluster with this configuration and analyzes the performance of Optane-based all-flash Ceph arrays. Various tunings are also discussed to improve Ceph performance on Optane drives.
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- A discussion of new overclocking capabilities for Intel Core processors like per-core overclocking and AVX ratio offset.
- Details on motherboard technologies from ASUS that enhance overclocking, like the ROG OC Panel and microcontrollers.
- An explanation of overclocking options for Intel 6th generation Core processors using the Intel Z170 chipset, including unlocked ratios and memory overclocking.
The document discusses tools and technologies for overclocking, like the Intel
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Please like and share my presentation if you feel like anyone needs it. Please comment down if you have any doubt. I will try to answer all of your queries. You guys are the best. Thank you.
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The document discusses Intel's Core 2 family of dual-core and quad-core 64-bit processors. Key points:
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This document provides details about a course on parallel and distributed computing systems. It discusses why studying parallel computing is important due to technological shifts toward multi-core processors. The course will cover foundations of parallel algorithms and programming, and provide hands-on experience using parallel hardware. Students will need basic knowledge of computer architecture and programming to succeed in the course.
This document provides an overview of a new CPU capability called Intel® Speed Select
Technology – Base Frequency (Intel® SST-BF), which is available on select SKUs of 2nd
generation Intel® Xeon® Scalable processor (formerly codenamed Cascade Lake). The
document also includes benchmarking data and instructions on how to enable the
capability.
Value propositions of this capability include:
• Select SKUs of 2nd generation Intel® Xeon® Scalable processor (5218N, 6230N, and
6252N) offer a new capability called Intel® SST-BF.
• Intel® SST-BF allows the CPU to be deployed with an asymmetric core frequency
configuration.
• The placement of key workloads on higher frequency Intel® SST-BF enabled cores
can result in an overall system workload increase and potential overall energy
savings when compared to deploying the CPU with symmetric core frequencies
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Taking AI to the Next Level in Manufacturing.pdfssuserfac0301
Read Taking AI to the Next Level in Manufacturing to gain insights on AI adoption in the manufacturing industry, such as:
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2. Which barriers stand in the way of AI adoption.
3. How data quality and governance form the backbone of AI.
4. Organizational processes and structures that may inhibit effective AI adoption.
6. Ideas and approaches to help build your organization's AI strategy.
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Fueling AI with Great Data with Airbyte WebinarZilliz
This talk will focus on how to collect data from a variety of sources, leveraging this data for RAG and other GenAI use cases, and finally charting your course to productionalization.
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We will explore the capabilities of AI in understanding XML markup languages and autonomously creating structured XML content. Additionally, we will examine the capacity of AI to enrich plain text with appropriate XML markup. Practical examples and methodological guidelines will be provided to elucidate how AI can be effectively prompted to interpret and generate accurate XML markup.
Further emphasis will be placed on the role of AI in developing XSLT, or schemas such as XSD and Schematron. We will address the techniques and strategies adopted to create prompts for generating code, explaining code, or refactoring the code, and the results achieved.
The discussion will extend to how AI can be used to transform XML content. In particular, the focus will be on the use of AI XPath extension functions in XSLT, Schematron, Schematron Quick Fixes, or for XML content refactoring.
The presentation aims to deliver a comprehensive overview of AI usage in XML development, providing attendees with the necessary knowledge to make informed decisions. Whether you’re at the early stages of adopting AI or considering integrating it in advanced XML development, this presentation will cover all levels of expertise.
By highlighting the potential advantages and challenges of integrating AI with XML development tools and languages, the presentation seeks to inspire thoughtful conversation around the future of XML development. We’ll not only delve into the technical aspects of AI-powered XML development but also discuss practical implications and possible future directions.
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GraphRAG for life science domain, where you retriever information from biomedical knowledge graphs using LLMs to increase the accuracy and performance of generated answers
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UiPath Test Automation using UiPath Test Suite series, part 6DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 6. In this session, we will cover Test Automation with generative AI and Open AI.
UiPath Test Automation with generative AI and Open AI webinar offers an in-depth exploration of leveraging cutting-edge technologies for test automation within the UiPath platform. Attendees will delve into the integration of generative AI, a test automation solution, with Open AI advanced natural language processing capabilities.
Throughout the session, participants will discover how this synergy empowers testers to automate repetitive tasks, enhance testing accuracy, and expedite the software testing life cycle. Topics covered include the seamless integration process, practical use cases, and the benefits of harnessing AI-driven automation for UiPath testing initiatives. By attending this webinar, testers, and automation professionals can gain valuable insights into harnessing the power of AI to optimize their test automation workflows within the UiPath ecosystem, ultimately driving efficiency and quality in software development processes.
What will you get from this session?
1. Insights into integrating generative AI.
2. Understanding how this integration enhances test automation within the UiPath platform
3. Practical demonstrations
4. Exploration of real-world use cases illustrating the benefits of AI-driven test automation for UiPath
Topics covered:
What is generative AI
Test Automation with generative AI and Open AI.
UiPath integration with generative AI
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
3. One Page Summary
Expensive middleware:
• is priced per core differently for different processors;
• its costs overshadow server & operating system costs.
1. Assess using Performance per Weighted Core
(P/WC) rather than Performance per Core.
2. The observed best to worst ratio exceeds 7x in one case.
3. Results vary not only with middleware and application,
but also with the scale.
4. For TPC-C on Oracle DBMS, the Hyper-threaded
XEONs have the best:
• P/WC rating;
• Clock-independent architecture:
P/WC per GHz.
5. For TPC-C on Oracle, similar results come from using
IBM’s PVU rather than Oracle’s Core Weighting Factor.
See below for
TPC-H and SAP
results as well.
3
4. Processor Selection For Optimum Middleware Price / Performance
One Page Summary
dakra137 at gmail.com
Expensive middleware:
• is priced per core differently for
different processors, servers,
etc;
• its costs overshadow server &
operating system costs.
1. Assess using Performance per
Weighted Core (P/WC) rather
than Performance per Core.
2. The observed best to worst ratio
exceeds 7x in one case.
3. Results vary not only with
middleware and application, but
also with the scale.
4. For TPC-C on Oracle DBMS, the
Hyper-threaded XEONs have the
best:
• P/WC rating;
• Clock rate-independent
architecture:
P/WC per GHz.
5. For TPC-C on Oracle, similar
results come from using IBM’s
PVU rather than Oracle’s Core
Weighting Factor.
6. For TPC-H on Oracle:
• Itanium
• Top @ 10,000
• Bottom @ 3,000 and 1,000
• Sparc
• Top (along with Power) @
3,000
• 2nd @ 10,000 and 1,000
• Power
• Top @ 3,000
• Hyper-threaded Xeon
• Top @ 1,000
7. SAP on Oracle
• Hyper-threaded Xeon on top
8. SAP on DB2
• Power7 on top
4
5. Acknowledgements
I wish to thank:
• The Transaction Processing Council and
SAP for making it so easy to acquire
benchmark results in readily usable form;
• Oracle and IBM for making their Core
Weighting Factor and Processor Value
Unit Tables readily available;
and especially,
• All the staff at all the companies who
implemented, tuned, measured, and
published the TPC and SAP benchmarks. 5
6. Key Question
How do you take into account
“Core Weighting Factors,”
“Processor Value Units,” etc.
when looking to pick a
processor to run EXPEN$IVE
middleware?
6
11. Answer #2a
That really does depend on:
• the middleware,
• the application, and
• its scale.
11
12. Answer #2b
This case study
considers:
• Middleware:
Oracle DBMS
• Applications:
•TPC-C
•TPC-H
TPC-H scales:
•1,000
•3,000
•10,000 12
13. Key Points
Middleware $ >> Everything else that
varies e.g. Server
HW & OS
This case study avoided:
• Exact pricing, for the reason above
• Performing benchmarks
• Constraints on publishing results
13
17. Key Point
Don’t be mislead by the quantities of
benchmarks!
The quantity of entries represents the
willingness of vendors to perform
benchmarks and publish results. All it
shows is consistency even as other
elements may vary, such as chipset,
SAN attachment, storage subsystem, etc.17
19. Architecture Analysis
For TPC-C the Hyper-threaded XEONs come out on top
because of performance, advantageous core weighting
factor, and clock rate.
The Power 6’s are next, due to sheer clock rate, in spite of heaviest
weighting.
The SPARC T3 would still be in the top 20 chart, ahead of the
some of the XEONs, even if it had the same weighting factor (.5
rather than .25) as the XEONs.
The best Itanium result compares closely to the Power5 results.
While the best XEON rating is 158K, the Itanium results vary from
58K down to 45K TpMC/WC rating units.
19
20. Source of Top Xeon’s Rating
Cache? No, the top three outperformed the
Xeon’s with larger cache per core and larger
total cache. 2MB per core was enough here.
Clock rate? No, the top three
outperformed the Xeon’s with higher clock
rates.
Hyper-threading? YES!
Core Weighting Factor? YES!
20
25. Analysis of TPC-H Results
TPC-H Scale Range of Results
10,000 1:2.4
3,000 1:5.6
1,000 1:7.4
Selecting a suboptimal processor
for TPC-H could increase costs
by up to 7.4x.
25
26. Analysis of TPC-H Results
Scale really matters!
• Itanium
• Top @ 10,000
• Bottom @ 3,000 and 1,000
• Sparc
• Top (along with Power) @ 3,000
• 2nd @ 10,000 and 1,000
• Greater gaps between groups of results @ 10,000 and 1,000
than @ 3,000
26
32. Clock Rate Will Grow
Compare architectures.
Factor out clock rate, so you can
estimate new higher clock rate
chips’ performance.
Use:
Performance per Weighted
Core per GHz 32
37. TPC-C Ranking Shifts Due to
Alternative Weightings
Server CPU Type
Order due to Oracle
Core Weighting
Factors
Order due to IBM
Processor Value
Units
Order
Difference
Intel Xeon Processor X5570 2.93GHz 1 1 0
Intel Xeon E5520 2.27 GHz 3 4 -1
IBM POWER6 - 4.7 GHz 4 3 1
Intel Xeon X5650 6-core 2.66GHz 5 5 0
IBM POWER5+ - 2.2 GHz 6 7 -1
SPARC T3 1.65GHz 7 31 -24
Intel Xeon Quad-Core X5460 - 3.16 GHz 8 6 2
IBM POWER5 - 1.9 GHz 9 12 -3
IBM POWER5 - 1.9 GHz 10 15 -5
IBM POWER5 - 1.9 GHz 12 18 -6
Intel Itanium2 Dual-Core - 1.6 GHz 13 8 5
Intel Xeon X7460 - 2.67 GHz 14 9 5
Intel Xeon X5355 - 2.66 GHz 17 13 4
Intel Itanium2 Dual-Core - 1.6 GHz 18 14 4
Intel Xeon QC 5440 - 2.83 GHz 19 17 2
Similar rows omitted 37
38. Different Architecture
Q: What will core weighting
factors and PVU’s be for the new
AMD Bulldozer processors?
(They are somewhat less than 2 cores per
processor building block.)
A: I don’t know.
38