1) The document discusses requirements for evaluating the global robustness of digital apparatus through both predictive simulation and experimental testing. 2) It describes the need for accurate models, powerful simulation tools, and experimental validation to reliably predict issues like signal integrity, electromagnetic interference, and susceptibility to faults and noise. 3) The THRIS environment aims to meet these requirements through a standardized hardware and software testing platform that integrates commercial simulation tools with customized interfaces, enabling both predictive analysis and experimental validation of robustness for digital designs.

1. Predictive versus Experimental
Approach for the Evaluation of Global
Robustness of Digital Apparatus
Piero Belforte, Paolo Fogliati
Luca Giacomello, Flavio Maggioni CSELT
Luigi Bragagnini Hewlett Packard
Carla Giachino, Emmanuel Leroux High Design Technology
Flavio Canavero Polytechnic of Turin

2. Outline
• Hardware robustness issues
• Tool requirements for testing hardware robustness
• Validation requirements for predictive tools
• The THRIS environment
• Validation examples
• THRIS application examples

3. Achieving Hardware Robustness: Key Issues
Hardware design phase
- signal integrity optimization (ringing, crosstalk, ground bounce, power supply
distribution analysis), timing problem control
- filtering/shielding optimization (EMI simulations)
- reliability evaluation (components, architectural conceps, thermal analysis)
Hardware/Software Integration phase
- fault insertion, noise injection, experimental EMI precompliance tests
EMC qualification phase
- emission/susceptibility conformity tests
Overall Fault Tolerance Verification phase
- fault insertion
Installation phase
- environment interaction evaluation (grounding, shielding, EMI tests)

4. Signal Integrity
• Most critical to manage:
– modeling for high speed/EMI
– simultaneous switching noise
• Less critical to manage:
– ringing/reflection control
– propagation delay evaluation
– crosstalk control
References:
A High-Performance Environment for Modelling and Simulation of Digital Systems - 1993 HP
High Speed Digital Systems Design & Test Symposium
Advanced Simulation and Modeling for Telecom System Hardware Design - 1994 HP
ATM/Broadband Design Symposium

5. Fault Insertion / Noise Injection
Fault Insertion: is a procedure to verify the behavior of an apparatus
in case of hardware faults
Noise Injection: is a procedure to verify noise margins within the
apparatus
– Typical procedure for physical fault insertion:
• put the system in normal operation
• introduce the fault: verify the system behavior (alarms, reconfiguration, etc)
• remove the fault: verify the system behavior (manual/automatic recovery)

6. Hardware Reliability Prediction
A “parts count” methodology applicable at early stage
“Early” evaluation of the project, for reliability fast predictions
Prediction methodology applicable to existing
Accurate prediction products, when complete data about electronic
devices used in the system are available in the CAD
environment

7. Requirements for a Reliable SI/EMI
Simulation
• Accurate modelling techniques
• Real exploitability of the simulation tool:
• powerful simulation engine (speed and complexity
management)
• integrability in the design flow
• customizability
• Experimental validation

8. Accurate Modelling
A good prediction requires accurate models of components
Data supported by Enough for low-speed
IBIS standard (< 100MHz) applications
IBIS
+ Necessary for high-speed
( > 100MHz), EMI
BTM*
* BTM= Behavioral Time Modelling

9. Why Accurate Models are
Required for EMI Prediction?
Driver waveform spectrum Radiated spectrum

10. Requirements of the Simulation Tool
• Simulation speed
• Taking into account all the effects at the same time
• Customizability and customer support
• Transparency on the applied methods

11. Requirements for EMI aspects
• Adequate validation environment
• Knowledge of the physical basis of the predictive algorythm
adopted inside the software
• Knowledge of the occurring EM phenomena

12. Considerations on the Choice of the
EMI Prediction Method
complex PCB configurations SIMPLIFIED
can be idealized and analyzed BUT models leads to
with efficient methods in the approximations
spectral domain
RIGOROUS models require
simple PCB configurations
can be fully analyzed with long computational times
BUT
rigorous 3D full-wave and are difficult to extend
methods as MoM, FDTD, to complex situations
finite elements method

13. Considerations on the Choice of the
Method: Possible Solution
A unique method is Solution adopted;
not available yet HYBRID METHOD
Analytical formulation
where enough Good trade-off
between accuracy
Numerical method ( PEEC) and simulation time
where necessary

14. Knowledge of the Occurring Phenomena When
Comparing Simulated and Measured Radiated Field
knowledge of the
simulation algorithms limitations
Definition of the best experience of
simulation setups
+ the designer
evaluation of the systematic errors of the simulation

15. CSELT’s EMC Laboratory Layout

16. Objective of an EMC Laboratory
TEST ACCURATE
RESULTS RIPETIBLE
REPEATABLE
TEST ENVIRONMENT

17. NSA: Basic Principles
Ideal test site
Semi Anechoic
Chamber (SAC)

18. NSA: Volumetric Measurement Method
4m
Ar
At
h2
h1
1m
d
D

19. SAC Performance
Measured NSA
THEORETICAL NSA OF AN IDEAL SITE SAC MEASURED NSA
NSA 5
30 4
25 3
20
2
15
1
10
DEVIATION[dB]
5
0
0 -1
-5 -2
- 10 -3
- 15 -4
- 20
-5
30 40 50 70 90 120 160 200 300 500 700 900
30 10
0 20
0 10
00
Frequency ( MHz )
F E UN YMz
R Q E C [ H]

20. Commonality Requirements
The tool must implement a common test
methodology for both manufacturers and their
clients
- design and integration tool for manufacturers
- incoming qualification and quality monitoring tool for clients

22. THRIS
• Hardware/Software test environment
• Hardware: standard workstation, standard instrumentation.
Partner: HP
• Software: integration/customization of commercial software for both
predictive and experimental issues.
• Custom Front-end (CSELT patented)
• THRIS validation is performed in CSELT laboratories
• New specifications from THRIS User Group (TUG)
• During „97: New functionalities added (reliability,thermal,EMC)

23. THRIS Functionalities (today)
• Modeling environment (including TDR)
• Signal integrity prediction
• EMI prediction (radiated/conducted emission,conducted susceptibility)
• EMI performance optimization (What-If analysis)
• Reliability evaluation (RAPSODIA, METRICA)
• Fault injection (pin forcing technique)
• Noise injection
• Electrical/thermal monitoring
• EMI precompliance analysis (near-field, common mode currents,
conducted susceptibility)

24. Some THRIS Validation Examples
- Radiated emissions (differential/common modes)
- Conducted susceptibility
- Fault insertion
- Noise injection

25. Radiated Emission Tool Validation
(Test vehicle #1)
Line length = 20 cm
Line imped. = 50 ohm
Top view pcb thickness=1.6mm
Er = 4.5
PCB size = 20x30 cm
50 ohm coax cable
Connector
Bottom view Battery
pack
Termination
Ground plane Oscillator PCB
Copper tape
Shielded oscillator

26. ECL Oscillator Model
V
I
Logic “1”
Logic “0”
Constant R
zone
Varying R
zone
GND
Static VI characteristic S_param
STF DTF Vo
Package

Equivalent Thevenin
Output stage of the circuit of the driver
ECL driver
-0.85
-1
Dynamic characteristic

27. Validation of ECL Oscillator Model
120
1 2
S param. 100
simulation
80
Vo
dBuV/m
V(2) 50 measure
60
40
20
0
344
206,4
481,6
619,2
756,8
825,6
68,8
Electrical model
frequency [MHz]
of the ECL driver
Comparison between the spectra of
measured and simulated output
waveform V(2) of the ECL driver
with a 50ohm termination

28. Typical Measurement Set-up
shielded
oscillator
h
10 m
H

29. Comparison Between
Measurements and Simulations
Frequency [MHz]
68,8
Measurements [dBuV/m]
22,47
Simulation [dBuV/m]
21,67
H=1m
206,4 37,38 35,87 h=1-4m with a 0.5m step
344 41,73 42,22
481,6 38,61 38,40 ECL shielded oscillator
619,2
756,8
31,88
32,61
35,60
30,05
Microstrip load = open
894,4 N.A.* 26.82
frequenza misura simulazione mis+4 mis-4 misura
68,8 22,47 21,67 22,47
206,4 37,38
50 35,87 41,38 33,38 37,38
344 41,73
40 42,22 45,73 37,73 41,73
dBuV/m
481,6 30
38,61 38,40 42,61 34,61 38,61
619,2 20
31,88 35,60 35,88 27,88 31,88
756,8 10
32,61 30,05 36,61 28,61 32,61
0
h
894,4 26,7 2,4 H
68,8
344
206,4
481,6
619,2
756,8
894,4
Freq(MHz)
Esempio in cui:
simulation
measure
* Measure under noise level

30. Common Mode Case Study:
PCB alone
35,00
H=1.36m
30,00
h=1-4m with a 0.5m step
25,00
CMOS 10MHz shielded oscillator
Microstrip load = open
dBuV/m
20,00
15,00
Antenna polarization = horizontal
10,00
5,00
0,00
100
110
120
130
140
150
160
170
180
50
60
70
80
90
simulation frequency [MHz]
measure
h
H

31. Common Mode Case Study:
PCB + attached cable
frequency (MHz) Simulation Measurement
50 10,30 12,23
H=136cm
70 18,64 20,01 h=1-4m with a 0.5m step
90 21,52 21,82
100 22,83 23,76 CMOS 10MHz shielded oscillator
120 27,15 31,71
140 35,92 36,27 microstrip load = open
160
180
34,29
34,04
29,98
28,24
Cable length = 60cm
Cable termination = open
40,00
Antenna polarization = horizontal
35,00
simulation
30,00
25,00
measure
dBuV/m
20,00
15,00
10,00
5,00
H
0,00 h
110
130
150
170
50
70
90
frequency [MHz]

32. Susceptibility Analysis Example
N
5 U1
P1_8
+
6
P3_2 -
P3_8
P3_1
Distributed ground

33. Measurement Setup
HP54750 DSO
TDR
TR3 2 1
flexible coax. cable
HP8648C
Power
added ground plane PCB under test
splitter

34. Measurement/Simulation Comparison
900MHz residual noise on comparator inputs
V [mV] 200.00
U1_6 meas.
150.00
U1_6 simul.
100.00
50.00
0.00
-50.00
-100.00
-150.00 U1_5 simul. U1_5 meas.
-200.00
25.00 25.50 26.00 26.50 27.00 27.50 28.00 28.50 29.00 29.50 30.00 TIME[nS]

35. Pin Forcing: Why Simulation is Needed
1 cm
Driver 3
R
7V e
Actual signal at location 1 6V c
and 2 in normal conditions 5V e
4V i
3V v
2V e
1V r
7V 0V s
-1 V 1
6V 0 10 20 30 40 50 60 2
5V TIME[nS]
location 2
4V 7V
3V location 1 6V location 1
2V 5V
1V 4V
0V 3V
-1 V 2 V location 2
0 10 20 30 40 50 60 1V
TIME[nS] 0V
-1 V
Residual noise measured at -2 V
0 10 20 30 40 50 60
location 1 and 2 when a THRIS TIME[nS]
stuck_at_0 is applied in 1
Actual signal at location 1 and 2
after one inverter stage

36. Pin Forcing: High Speed Systems
32 155Mbit/s 32 155Mbit/s
input streams output streams
Stage A Stage B Stage C
0.00 V
Fault
STM1 INPUT STREAM (155 Mbit/s)
Description: -1.30 V
3 Boards + backplane -2.00 V
0.00 V
32 155Mbit/s streams
6 16x16 switching matrices -1.30 V
FAULTY NODE (FIRST STAGE OUTPUT)
-2.00 V
0.00 V
THRIS simulation model: FAULTY OUTPUT STREAM
50000 circuit elements -1.30 V
35000 nodes -2.00 V
0.00 V
20000 timepoints OFF ON OFF ON
20‟ simulation time on typ. ws. FAULT CONTROL
-2.00 V
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
TIM E[uS]

37. Noise Injection: Noise Margin Evaluation
-0.5 V
Normal operation
-0.7 V
-0.9 V
5mA current injection
-0.5 V
-1.1 V
-0.7 V
-1.3 V
-1.5 V
-0.9 V
12mA current injection
-0.5 V
-1.1 V
-1.7 V
-0.7 V
-1.3 V
-1.9 V -0.9 V
-1.5 V
0.0 2.0 4.0 6.0 8.0 10.0 12.0
-1.1 V
TIME[nS]
-1.7 V
-1.3 V
-1.9 V
-1.5 V
0.0 2.0 4.0 6.0 8.0 10.0 12.0
N TIME[nS]
-1.7 V
ecl interconnection
-1.9 V
0.0 2.0 4.0 6.0 8.0 10.0 12.0
TIME[nS]
output testpoint

38. Pre-compliance Near-Field Testing
ROM card HP 8590EM EMC Analyzer
Preamplifier
HP-IB cable
to THRIS
DUT
Near field probe

39. Pre-compliance Common Mode
Current Testing
ROM card HP8590EM EMC Analyzer
Preamplifier
HP-IB cable
to THRIS
CABLE
UNDER
TEST
HP 11967A

40. Thermal Monitoring

41. Conclusions
• EMI behavior of electronic equipment must be optimized in early design
stage. Simulation is the key.
• The simulation tool should be accurately validated versus measurements in
suitable site (e.g. accreditated EMC labs).
• Reliable EMI simulations require accurate SI models based on wide -band
measurements on components (e.g.: TDR, network analyzer, ecc).
• Measurements are still mandatory for the certification phase. If some
problems are detected, corrective actions can be experimented by means of
simulation (e.g. What-if analysis)
• Specific EMI measurements executed after installation can identify
problems due to the environment impact, even if the device under test has
been already certified.

42. THRIS Solutions
WHO BENEFITS
Designers, R&D Optimized design,
THRIS_SI engineers redesign cycle reduction
Hardware/software Increased tests
THRIS_IG system integration coverage,
engineers increased system level
robustness
THRIS_EMC Designers, R&D
engineers, EMC EMI problems found and
specialists fixed at design stage

43. THRIS Resources
THRIS_SI THRIS_IG THRIS_EMC
Workstation x x x
VEE x x
VXI, Front_end x
EMC instruments x
THRIS manager x x x
Fault insertion test suite x
Post-layout analysis package x x x
Crosstalk, bouncing analysis x
EMI radiated emissions analysis x
What-IF analysis opt. opt. opt.
Modeling development suite opt. opt.

44. THRIS Application Example
Design of a high speed board (ATM switch)

45. THRIS Application Example
Fault injection probes

46. THRIS Application Example
Qualification trials on a digital exchange

47. THRIS Application Example
Design verification of a telecom auxiliary apparatus

48. THRIS Application Example
Fault insertion trials on a SDH apparatus

49. THRIS Application Example
Signal monitoring inside a public telecom terminal